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5,918 Views
Registered: ‎01-28-2010

asynchronous reset makes component switching limits fail

I am creating a new post here since it relates to timing analysis better than to Spartan devices. The original post with details on the application is here http://forums.xilinx.com/xlnx/board/message?board.id=Spartan&thread.id=4777

 

I successfully managed to synthesize and place the design. The first FF is right next to the IOB and the next counter bits also nearby. BUFGs are not inserted, the IOB output is locally routed to the clock pin of the first FF.

I am having trouble though with constraining the design. In my understanding, I need the following constraints:

- PERIOD for the clock-to-be measured. This will make sure that the output of the first FF can get back to its input pin (T-FF) before the next edge arrives. The next FFs in the counter are not important, since if the first meets this constraint, it is safe to assume that the next ones (with twice the clock period) will also meet it.

- TIG between the counter FFs (running on the gated clocks of the previous FF) and the count readout FFs (running on the system clock). I will make sure that the readout happens only when all the counter bits settled.

 

The trouble is with the asynchronous reset of the count FFs. I absolutely need reset for these and since they have gated clocks, it needs to be asynchronous. It is correctly synthesized being connected to the CLR pins.

I produce this reset for one full system clock period (it is synchronous with the system clock, around 60 ns long pulse). However, I am getting the following constraint failure:

 

 Component Switching Limit Checks: TS_G5_CLKDS = PERIOD TIMEGRP "G5_CLKDS" 400 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: -0.692ns (period - (min low pulse limit / (low pulse / period)))
  Period: 2.500ns
  Low pulse: 1.250ns
  Low pulse limit: 1.596ns (Trpw)
  Physical resource: frqCnt4<0>/SR
  Logical resource: Inst_FrqCnt4/cnt_0/SR
  Location pin: SLICE_X66Y39.SR
  Clock network: ctlTmrRst

 

It seems to me that ISE complains about the pulse length of the reset signal (Trpw) on the SR pin of the first FF driven by the clock-to-be measured. Again, the reset should be asynchronous to this clock and asserted to a full system clock period, which is larger than Trpw. Am I missing something here?

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Xilinx Employee
Xilinx Employee
5,880 Views
Registered: ‎11-28-2007

Re: asynchronous reset makes component switching limits fail

How is the reset signal for frqCnt4<0> is generated?
Cheers,
Jim
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5,877 Views
Registered: ‎01-28-2010

Re: asynchronous reset makes component switching limits fail

ctlTmrRst is the reset for frqCnt<0>. It is a registered output of a state machine, running on the system clock (50 MHz).
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