08-17-2017 03:26 AM
In post :
I see that you have mentioned following :
create_generated_clock -name clk1_post -source [get_pins BUFGMUX_inst/I0] -combinatorial [get_pins BUFGMUX_inst/O]
create_generated_clock -name clk2_post -source [get_pins BUFGMUX_inst/I1] -combinatorial [get_pins BUFGMUX_inst/O] -add.
Quick clarification needed :
1) I believe we need to use -master_clock option too, otherwise Vivado (v2017.2) tool throws warning that no _master_clock is defined.
2) You are using -combinational flag because generated clock (out of BUFGMUX) is travelling through combinational logic of mux, right? And that input to this logic (of MUX) is a clock.
Something like :
In this case combo logic is mux.
a) But if we have simple AND gate of clock gating logic, then also same principle will hold true and we will need -combinational flag to create_generate_clock at output of AND gate w.r.t. the clock coming to inputs of AND gate, right?
b) What if, if the input to mux is another generated_clock based on some source clock. There also can we use -combinational flag? Circuit is something like :
But there is an AR to put constraints :
And there i don't see any -combinational flag in constraints. Can you please let me know what am i missing here?
08-25-2017 12:45 AM
I created this new post because the previous post, on which i queried, was closed. And i thought you might not get notification because previous post is closed. But i think i was wrong and you got notification there.
I have updated my reply on same post (https://forums.xilinx.com/t5/Timing-Analysis/Vivado-and-BUFGMUX-timing/m-p/786960#M12166).
Thanks and Regards,