UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
5,323 Views
Registered: ‎01-22-2015

clock-crosser and combinational logic

Jump to solution

In a post here, Avrum explains that feeding a clock-crosser (ie. synchronizer) directly from combinational logic can “break” the clock-crosser.

 

In VHDL, it is all too easy to use concurrent assignment statements like the following:

--------------

signal sigA, sigB, sigC : std_logic;

sigA <= sigB or sigC;      --VHDL concurrent assignment

process (sigB, sigC)       --process that equates to concurrent assignment shown above

begin  

   sigA <= sigB or sigC;

end process;

--------------

 

In this example, the concurrent assignment elaborates to combinational logic. So, if the result, sigA, is fed directly to a clock-crosser, then the clock-crosser will not work reliably.

 

In Vivado, is there an easy way to search for instances of clock-crossers being fed directly from combinational logic?

0 Kudos
1 Solution

Accepted Solutions
Guide avrumw
Guide
9,491 Views
Registered: ‎01-23-2009

Re: clock-crosser and combinational logic

Jump to solution

This is one of the many checks performed by the report_cdc command. 

 

Avrum 

View solution in original post

0 Kudos
5 Replies
Guide avrumw
Guide
9,492 Views
Registered: ‎01-23-2009

Re: clock-crosser and combinational logic

Jump to solution

This is one of the many checks performed by the report_cdc command. 

 

Avrum 

View solution in original post

0 Kudos
5,260 Views
Registered: ‎01-22-2015

Re: clock-crosser and combinational logic

Jump to solution

Avrum,

Thanks for introducing me to Vivado report_cdc.  I found excellent description of the tool in ug906 and in the Xilinx video here.

 

To be clear, my original comments should say that Vivado synthesis *optimization* causes the final elaboration for the VHDL concurrent assignment to be only a combinatorial logic block (ie. a LUT). -and, the register associated with sigA is “optimized out” (ie. absorbed into the LUT).   With sigA (and its register) gone, the LUT directly feeds the synchronizer, causing the problem referred to as “Combinatorial Logic (CDC-10)” by report_cdc.

 

After your warning about the CDC-10 problem some months ago, I have tried not to use concurrent assignments. Instead, I now (for example) place the sigA assignment statement inside a clocked process.  This prevents sigA from being optimized out.  Because of this, report_cdc found no CDC-10 problems in my project.

 

Incidentally, I find that I have already done the CDC-10 check (indirectly) by carefully writing the “set_max_delay -datapath_only” constraint for each clock-crossing.  As you explain elsewhere, this constraint is placed on the timing path that extends (in my example) from sigA to the first register in the synchronizer.  So, if synthesis had optimized-out sigA then I would have gotten a warning about an invalid path in my set_max_delay constraint.

 

Finally, as a test of report_cdc, I went back to using the VHDL concurrent assignment statement for sigA and again found that the register for sigA was optimized out.  As expected, my set_max_delay constraint receives a synthesis warning (because sigA_reg does not exist).  However, report_cdc did not flag this clock-crossing with the CDC-10 error – or any kind of error!

 

Can you think of any reason why report_cdc would not catch my CDC-10 error?

 

Mark

0 Kudos
Highlighted
Guide avrumw
Guide
5,252 Views
Registered: ‎01-23-2009

Re: clock-crosser and combinational logic

Jump to solution

Mark,

 

I don't follow your question.

 

Whether your assignment is done in a concurrent assignment or in an un-clocked process it is combinatorial. So, in your examples, sigA is combinatorial regardless of which form you use - feeding that across clock domains is an illegal clock crosser.

 

To be clear - the following code is explicitly coding a combinatorial process...

 

process (sigB, sigC)       --process that equates to concurrent assignment shown above

begin  

   sigA <= sigB or sigC;

end process;

 

In order to be feed a clock domain crossing circuit, sigA must be a flip-flop, which means that it is assigned in a clocked process. If it is assigned in a clocked process [i.e. after a "if (rising_edge..."] then sigA is a flip-flop. There is no ambiguity in this - your RTL coding uniquely determines whether sigA is a register or the output of some combinatorial logic.

 

The only exceptions would be if you allow synthesis to modify your code through a specific number of optimizations:

  - FSM extraction

  - register balancing

  - (maybe one or two others I can't think of)

 

Both of these can be controlled via synthesis directives - you can put a DONT_TOUCH on the flip-flop if you are concerned about register balancing, and you can set the FSM style to user encoded for any FSM that directly feeds a clock crossing circuit...

 

Avrum

0 Kudos
5,240 Views
Registered: ‎01-22-2015

Re: clock-crosser and combinational logic

Jump to solution

Avrum,  Thanks for your reply!

 

I understand the *right* things to do (ie. forming sigA inside a clocked process and maybe using DONT_TOUCH) in order to get the sigA_reg register which will properly feed the synchronizer.

 

However, as a test for report_cdc, I purposely did the *wrong* thing by forming sigA inside an unclocked process.  This caused my synchronizer to be fed by a LUT and report_cdc did not flag this as a problem

 

The schematic below is from my project where I purposely did the *wrong* thing to test report_cdc. Note how LUT3 directly feeds the two-flip-flop synchronizer called SYNC1_2FF_373.   Should report_cdc have flagged this circuit as having the CDC-10 problem?  I think yes.

CDC1.jpg

0 Kudos
Guide avrumw
Guide
5,209 Views
Registered: ‎01-23-2009

Re: clock-crosser and combinational logic

Jump to solution

One would think so...

 

If it is not, then this could be a bug in the report_cdc command.

 

If you have webcase access, you should submit this as a bug report. If not, then if you can post your example project, someone can submit the case for you.

 

Avrum

0 Kudos