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oh__oh
Newbie
Newbie
318 Views
Registered: ‎01-19-2021

constraints

I have question about clock constraints in VIVADO 2020.2

 

my verilog code is here :

module top(
LED,clk
);
input clk;
output reg [3:0] LED = 4'b0;
reg [31:0] counter = 32'b0;

 

always @(posedge clk) begin

if(counter==32'd125000000) begin

LED <= LED +1;

counter <= 0;

end else begin

counter <= counter +1;

end

end

 

and constraints is  here : 

set_property PACKAGE_PIN D18 [get_ports {LED[3]}]
set_property PACKAGE_PIN G14 [get_ports {LED[2]}]
set_property PACKAGE_PIN M15 [get_ports {LED[1]}]
set_property PACKAGE_PIN M14 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10 -name clk [get_ports clk]

 

and there is error message :

[Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.

 

Q1) I don't know why I get an error message.

Q2) is there anything wrong with my constraints file?

 

my board is zybo-z7-10 and enviroment is VIVADO 2020.2

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1 Reply
miker
Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎11-30-2007

@oh__oh 

I ran your code and constraints targeting the Zybo-Z7-10 and it had timing constraints present and passed:

forums_zybo_timing.png

I attached my Vivado 2020.2 Project Archive for you to review.

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