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Observer
Observer
6,738 Views
Registered: ‎11-23-2010

controlling hold time using offset out constraint ...

Hi,

 

I have a question reg. setting the hold time for FPGAs using offset out constraint.

 

I have a design that does fine in bhv sim and post PAR sim. all the timing constraints etc. are met. Design runs at 40MHz.

 

Now in the timing report, I see that the min allowable offset out time is 4.2 ns and currently my UCF file has the constraint of  OFFSET = OUT 5 ns AFTER CLK; so this works fine. But in the post PAR sims, I still see a delay between the rising edge of the clk and the o/p signal as 4.2 ns and not 5 ns. So my questions are -

 

(1) 

I was told that in post PAR sims, the UCF constraints are not taken, but only the delay values calculated in PAR, hence I dont see a 5ns delay. Is my understanding correct?

 

(2)

Also, suppose I want to give my o/p signal to a chip that has a hold time of ... say 6 ns, and uses the same clk as that of the FPGA. So now, if I give the o/p signal directly, then since the offset out constraint is 5 ns, it might lead to a metastability issue. So will it be enough to increase the offset out to ... say 7 ns in the UCF file?

 

(3)

Or because the tool can do 4.2 ns as offset out, which is better than the delay I specify in the UCF file, it will stick to 4.2ns and so now, I will have to add buffer, IODELAY primitive to meet the hold time of my chip?

 

(4)

since I dont see the offset out constraint take effect in post PAR sims, I am just a bit concerned that if I do specify an offset out constraint, it does take effect on the o/p pin, after the specifed delay or am I missing something here of if I need to do something special for this?

 

Please confirm/let me know ...

 

Thanks,

Z.

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Historian
Historian
6,707 Views
Registered: ‎02-25-2008

Re: controlling hold time using offset out constraint ...


@zubinkumar wrote:

 

(1) 

I was told that in post PAR sims, the UCF constraints are not taken, but only the delay values calculated in PAR, hence I dont see a 5ns delay. Is my understanding correct?


 

 

UCF constraints are never used in simulation (either functional or post-route timing). For the former all delays are delta delays. For the latter, all delays are the back-annoted actual timing values determined by the tools. So if the real delay is 4.2 ns then that's what gets used, not the 5 ns you specified in the constraint.

 


(2)

Also, suppose I want to give my o/p signal to a chip that has a hold time of ... say 6 ns, and uses the same clk as that of the FPGA. So now, if I give the o/p signal directly, then since the offset out constraint is 5 ns, it might lead to a metastability issue. So will it be enough to increase the offset out to ... say 7 ns in the UCF file?

 

(3)

 

Or because the tool can do 4.2 ns as offset out, which is better than the delay I specify in the UCF file, it will stick to 4.2ns and so now, I will have to add buffer, IODELAY primitive to meet the hold time of my chip? 

 


 

Changing the OFFSET OUT does not change the delay. OFFSET OUT only tells you whether the output delay meets the bound you specified. In this case, the output delay is always 4.2 ns; extending OFFSET OUT doesn't change that.

 

So if you have specific setup and hold requirements on a downstream device, you need to write your constraint to match reality. Then you need to add appropriate delay to meet that reality, either with a delay on the clock, a delay on the data, or perhaps flipping the polarity of the clock or whatever. 

 

The point is that the tools won't set an output delay to ensure you meet the downstream requirements. You have to design that in.

 


(4)

since I dont see the offset out constraint take effect in post PAR sims, I am just a bit concerned that if I do specify an offset out constraint, it does take effect on the o/p pin, after the specifed delay or am I missing something here of if I need to do something special for this?


 

 

See above.

----------------------------Yes, I do this for a living.