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Observer
Observer
6,490 Views
Registered: ‎02-28-2013

data path slack across multiple clock domains [ZYNQ]

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I am using the Analog devices PL and their ZED system design where I have put in a block that can dump data into a 2D array set which then is clocked out of this 2D array on a new clocking domain.  There are many timing issues with their base system as it is without my interface block in the system as it is. 

I have tried several different strategies (implementation and synth) as well as changing how values are registered and assigned to get through timing slack issues. I've solved a fair number of them, however I am VERY new at timing closure and never really have done it before. 

I have the 2D array in my system to avoid using BRAMS as they are needed by other  part of the design. 

Is there any book or set of methods that are generally applied to solve issues with slack? 
The design also states critical errors that say no input delay and no output delay. Are these critical to the system calculating timing closure on slack? 
If so how do I calculate these?

I have attached my XDC file and the timing report.  If anyone can help or point out obvious errors the help is very much appreciated.

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Guide
Guide
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Registered: ‎01-23-2009

Re: data path slack across multiple clock domains [ZYNQ]

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My first question is that since I am using a few different clocking domains and transfering data between them all, I should set a max delay of roughly 10% less than the minimum of two clocking domain cells , right? Nearly all the data interchange happens via FIFO structures and the like. 

 

It is important to realize that every clock domain crossing (CDC) circuit is different. As such the constraints required on the CDC are also different. Some require skews of less than one source clock, some require skews of less than one destination clock and some require skews less than the smaller of the two (and some may even require something else).

 

In this context, I am very strongly advocate a more cautious "look at (and constrain) each CDC separately". I am very wary of any "clock to clock" blanket exceptions, and almost exclusively use path based exceptions - when doing this, I can tailor each exception to the CDC.

 

Furthermore, Xilinx IP all comes with constraints. So if you are using a clock crossing FIFO from the Xilinx IP catalog, it comes with the appropriate constraints for the CDC internal to the FIFO (and there is CDC in the full/empty generation logic associated with the FIFO). So if you use only Xilinx dual-clock FIFOs for your clock crossing, all (or at least most of) your timing exceptions should already be there, are written "safely" (path based rather than clock based) and should be correct - I would lean toward not supplementing these with "blanket" clock-to-clock constraints.

 

this path should be a false path as the reset signal us an async_default type of signal and will be held active for a significant ammount of time. Correct?

 

ABSOLUTELY NOT!

 

This is one of the most pervasive and dangerous common misconceptions in the digital design community. An "asynchronous reset" does NOT mean that it can be asynchronous to the system it is resetting - it means that the entry to the reset condition occurs asynchronously to the clock and even if the clock is not present. However, the deassertion of the reset MUST MUST MUST be done synchronous to the clock and must be timed as a normal synchronous timing path. Failure to do so can result in a system that fails to reliably exit the reset condition!

 

Take a look at this post on the timing requirements of asynchronous resets.

 

Avrum

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: data path slack across multiple clock domains [ZYNQ]

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You have only one clock domain.

 

How large is your 2D array?  For best timing use BRAM.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
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Registered: ‎02-28-2013

Re: data path slack across multiple clock domains [ZYNQ]

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I have quite a few actually as can be seen in the timing report. 

------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                      WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints
-----                                                                      -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk_fpga_0                                                                  -1.447    -1753.092                   3970                16844        0.051        0.000                      0                16844        1.020        0.000                       0                  8967
clk_fpga_1                                                                   3.583        0.000                      0                    2        0.282        0.000                      0                    2        0.264        0.000                       0                     5  
dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK           22.726        0.000                      0                  531        0.097        0.000                      0                  531       13.750        0.000                       0                   270
  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE       57.696        0.000                      0                    1        0.696        0.000                      0                    1       29.500        0.000                       0                     2  
i_system_wrapper/system_i/clk_wiz_0/inst/clk_in1                                                                                                                                                                         0.833        0.000                       0                     1  
  clk_out1_system_clk_wiz_0_0                                               -2.088     -999.479                   1336                 2380        0.059        0.000                      0                 2380       -0.944       -8.198                      28                  1365
  clkfbout_system_clk_wiz_0_0                                                                                                                                                                                            2.751        0.000                       0                     2  
rx_clk                                                                       1.512        0.000                      0                16436        0.051        0.000                      0                16436        5.270        0.000                       0                 12241
  s_clk_s                                                                   23.089        0.000                      0                   34        0.069        0.000                      0                   34       11.250        0.000                       0                    17  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                           To Clock                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                           --------                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
rx_clk                                                               clk_fpga_0                                                                 2.737        0.000                      0                   17
clk_fpga_0                                                           clk_fpga_1                                                                -0.952       -0.952                      1                    1        0.159        0.000                      0                    1
dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK         56.292        0.000                      0                   18        0.431        0.000                      0                   18
rx_clk                                                               clk_out1_system_clk_wiz_0_0                                               -2.538      -15.442                      8                    8       -1.282       -2.510                      2                    8  
clk_fpga_0                                                           rx_clk                                                                    -1.510       -1.510                      1                   14        0.158        0.000                      0                    1
s_clk_s                                                              rx_clk                                                                     5.254        0.000                      0                   25        1.296        0.000                      0                   25
clk_fpga_0                                                           s_clk_s                                                                   -0.149       -0.149                      1                    1       -1.842       -1.842                      1                    1  
rx_clk                                                               s_clk_s                                                                    6.093        0.000                      0                    4        1.161        0.000                      0                    4


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                         From Clock                                                         To Clock                                                               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints
----------                                                         ----------                                                         --------                                                               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                  clk_fpga_0                                                         clk_fpga_0                                                              -1.021    -1279.371                   3364                 5275        0.698        0.000                      0                 5275
**async_default**                                                  clk_out1_system_clk_wiz_0_0                                        clk_out1_system_clk_wiz_0_0                                             -1.070       -6.318                     17                   94        0.136        0.000                      0                   94
**async_default**                                                  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK       23.642        0.000                      0                  102        0.371        0.000                      0                  102
**async_default**                                                  rx_clk                                                             rx_clk                                                                   1.101        0.000                      0                 1757        0.314        0.000                      0                 1757
**async_default**                                                  s_clk_s                                                            s_clk_s                                                                 22.796        0.000                      0                    5        0.797        0.000                      0                    5  

 

The 2D array is a 16 layer 32 bit wide fifo. I need to avoid using BRAMs for this due to the rest of my design needing all of them.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: data path slack across multiple clock domains [ZYNQ]

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hi,

 

would that be possible to share the routed.dcp for further analysis?

 

--hs

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: data path slack across multiple clock domains [ZYNQ]

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Hi,

I have look into the timing report and my 1st observation is the design is under constraint.
There are few clock domain crossing are not constrained properly nd have unrealistic requirement of <0.5ns for setup which cannot be meet by tool. Those CDC paths might be either asynchronous as per design or if those have to be analyzed you need to specify proper exception constraints for example multi-cycle constraints and should have proper CDC circuit.

Also input and output delay constraints should be present for the design which evaluate the data validity/synchronization at input and output interface. This constraints are primary set of constraints.

Also there are few async_default groups you need to check those clock domains as well.

To understand more on timing refer below two UG:
UG 903 for timing understanding and constraints.
UG 906 for timing closure and recommended practice.

Thanks,
Yash
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Observer
Observer
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Registered: ‎02-28-2013

Re: data path slack across multiple clock domains [ZYNQ]

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@htsvn

Yes , https://www.dropbox.com/s/sbbmo15qfza080p/system_top_routed.dcp?dl=0

Thank you for your help!

 

 

@yashp

This is what I am not sure of how to do. I have read through both user guides and neither give any formula or indication on how to choose input/output delay for data signals or random clock sources. 

From what I read though, it seems that if there are clock crossing domains those need to be set as multi cycle transfers, and for asynchronous data paths (like reset) those need to be set as false paths, right? 

For example I have a reset coming from the sysrst block that has slack of -.183 and I should set that as a false  path, right? (this is the async_defult path)
Meanwhile if I have data going form one clock to another I should set that as a multicycle delay of rise/fall, right?

Thank you for all your help.

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Guide
Guide
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Registered: ‎01-23-2009

Re: data path slack across multiple clock domains [ZYNQ]

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Take a look at this posting on constraining Clock Domain Crossing circuits, including the posts referenced in this one.

 

Avrum

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Observer
Observer
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Registered: ‎02-28-2013

Re: data path slack across multiple clock domains [ZYNQ]

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@avrumw


Wow, thank you for those very insightful and well put together explanations. 

It leads me to two new questions however.

My first question is that since I am using a few different clocking domains and transfering data between them all, I should set a max delay of roughly 10% less than the minimum of two clocking domain cells , right? Nearly all the data interchange happens via FIFO structures and the like. 

The other question is regaurding reset signals coming from the sys_rstgen IP core. Because it has the slowest sync clock between all the AXI modules that need a reset signal, and this reset signal goes to a few places that are on different clocking schemes, this path should be a false path as the reset signal us an async_default type of signal and will be held active for a significant ammount of time. Correct? Or am I still a little off on the meaning of that?

I still am not sure how to constrain input and output delay however

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: data path slack across multiple clock domains [ZYNQ]

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My first question is that since I am using a few different clocking domains and transfering data between them all, I should set a max delay of roughly 10% less than the minimum of two clocking domain cells , right? Nearly all the data interchange happens via FIFO structures and the like. 

 

It is important to realize that every clock domain crossing (CDC) circuit is different. As such the constraints required on the CDC are also different. Some require skews of less than one source clock, some require skews of less than one destination clock and some require skews less than the smaller of the two (and some may even require something else).

 

In this context, I am very strongly advocate a more cautious "look at (and constrain) each CDC separately". I am very wary of any "clock to clock" blanket exceptions, and almost exclusively use path based exceptions - when doing this, I can tailor each exception to the CDC.

 

Furthermore, Xilinx IP all comes with constraints. So if you are using a clock crossing FIFO from the Xilinx IP catalog, it comes with the appropriate constraints for the CDC internal to the FIFO (and there is CDC in the full/empty generation logic associated with the FIFO). So if you use only Xilinx dual-clock FIFOs for your clock crossing, all (or at least most of) your timing exceptions should already be there, are written "safely" (path based rather than clock based) and should be correct - I would lean toward not supplementing these with "blanket" clock-to-clock constraints.

 

this path should be a false path as the reset signal us an async_default type of signal and will be held active for a significant ammount of time. Correct?

 

ABSOLUTELY NOT!

 

This is one of the most pervasive and dangerous common misconceptions in the digital design community. An "asynchronous reset" does NOT mean that it can be asynchronous to the system it is resetting - it means that the entry to the reset condition occurs asynchronously to the clock and even if the clock is not present. However, the deassertion of the reset MUST MUST MUST be done synchronous to the clock and must be timed as a normal synchronous timing path. Failure to do so can result in a system that fails to reliably exit the reset condition!

 

Take a look at this post on the timing requirements of asynchronous resets.

 

Avrum

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Observer
Observer
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Registered: ‎02-28-2013

Re: data path slack across multiple clock domains [ZYNQ]

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@avrumw

That would make sense, and I can see now where it would be implied in the other posts that you linked me to. 
That's not exactly what I want to hear, but then again when is it ever, haha.  It seems that I need to check all the CDC's and manage, constrain, or better implement them. Unfortunately I have a lot of them. 

I see where using the Xilinx FIFO CDC hardened implementations would be useful to me too, unfortunately I'm not sure if I can actually use them, but I think thats a problem for me. 

That again makes sense when explained like that, thank you very much (have you considered writing a book about this?) .

With that, I believe that since the reset must be at least deserted synchronously and it is going to many different AXI modules, these must have a max delay data path that allows for a multi-cycle delay of the reset signal being sent to all of my modules. 
Because I have so many, I believe that there are issues placing the reset signal close enough to where it needs to go and routing it to each module that needs to be reset. 

Thank you very much for all of this information, it's priceless. 

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