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Adventurer
Adventurer
111 Views
Registered: ‎02-13-2019

determining the speed of the submodules of a project

Hi, I'm Jose and I have the next doubt.

If I have a project composed of several modules, and I want to determine the speed of each of the modules that composed the project, I think that I need to determine the max freq of each module using the relation

fmax= 1/( clk period- WNS)

is that correct?

But the main doubt is: If I need to isolate each module, It means that in order to know the timing summary I need to implement it, so in order to implement every module do I need to connect every port to something?
I mean, if for example I have two registers connected back to back, and the output corresponds to a bus, do I need to have the output neccessarily connected to something (GPIO or another module) in order to implement it?
I ask this because if I need to determine the max freq of many components of a project it would be tedious to write code for connect every port of every module I hope to test.


thanks

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Xilinx Employee
Xilinx Employee
91 Views
Registered: ‎05-14-2008

Re: determining the speed of the submodules of a project

If you test those modules one by one, you can set each as top level (so don't need to make connections of all ports).

And you can run it in out_of_context mode, which is to set the Synthesis -mode option to out_of_context.

In this way, you can get the module run through Implementation.

However, when the module is set as top level, the Fmax you get is not the actual performance when it acts in the whold design.

What's more, below AR will help you understand the Fmax in Vivado.

https://www.xilinx.com/support/answers/57304.html

-vivian

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Xilinx Employee
Xilinx Employee
90 Views
Registered: ‎05-22-2018

Re: determining the speed of the submodules of a project

Hi @jose09621 ,

What i understood is, your requirement is for runnign each module saperately of an design.

I guess in order to achive that you can go got OOC flow(Hierarchical design flow). For detailed information please check below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug905-vivado-hierarchical-design.pdf

Thanks,

Raj

 

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Adventurer
Adventurer
44 Views
Registered: ‎02-13-2019

Re: determining the speed of the submodules of a project

@viviany, thanks for answer. What do you mean with " the Fmax you get is not the actual performance when it acts in the whole design"? if  I have a submodule working at 200 MHZ for example and I attach it to a bigger design that also works at 200MHz is it possible that the submodule won´t work at the 200MHz?

about the AR, what do the terms "given implementation" and "given architecture" mean?
the given implementation refers to the user described hardware? the given architecture refers to the FPGA part used?

@rshekhaw  thanks for answer, I've been reading it. I hope I don't need to use constraints on every submodule. Anyway I'll ask again if some doubts surge.


thanks

 

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