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distributed RAM: timing errror on read

Participant
Posts: 35
Registered: ‎03-15-2012

distributed RAM: timing errror on read

Hi,

 

I've problems defining the correct constraints for an asynchronous fifo. The clocks are not independend, they are derived with a very small difference. Applying a FROM TO constraint on the handshaking signals is not the problem and as long as i use block rams everything is fine. But the depth of the fifo is very small, so i like to use distibuted ram (16 depth, 39 bits wide). The STA now sees errors between the distributed ram and the register stage after them. The requirement is less than 0.6ns (same as the handshaking signal without the constraints).

 

The problem is, defining the correct FROM TO value, since the path from the ram to the register stage is only a part. The complete path should be from the adress registers, throught the distributed ram to the final register stage.

 

(it is the same if i use the coregen fifo-generator V9.3. The PG057 does not help.)

 

can anyone help?

 

thanks

Highlighted
Historian
Posts: 4,540
Registered: ‎01-23-2009

Re: distributed RAM: timing errror on read

In a distributed RAM read, there are actually two paths.

 

The first path is from the FFs that generate the read address through the DPRA bits of the RAM through the read data outputs to the RAM to the capture flops. Since you are using this as a FIFO, the read address should be clocked by the read clock, which should be the same clock used to capture the data. This path should be correctly constrained by the PERIOD constraint of the read clock.

 

However, there is a second path.

 

Lets assume that the read address is at address 0, and stays there for some time - you are continually reading the data at address 0. At the same time, on a given write clock, you perform a write to address 0 - this write is synchronous to the write clock. Since the content of the RAM has changed, and you are reading the location that has changed, then the data on the read data port will change slightly after the write clock. This is the second timing path; from the clock that performs the synchronous write of the DPRAM through the read data port to your read capture flops. It is this path that needs a FROM:TO - it is essentially a false path since the control circuitry of your FIFO explicitly prevents you from reading from the same location you are writing (but you should still use a FROM:TO DATAPATH_ONLY, not a TIG).

 

This second path does start at the clock of the dual port RAM and propagate to the capture FFs... The DPRAM is an odd beast - it is partly a synchronous element (the write) and partly a combinatorial element (the read).

 

Avrum

Explorer
Posts: 165
Registered: ‎04-13-2013

Re: distributed RAM: timing errror on read

[ Edited ]

Avrum's answer is great.

Michael

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Thanks for god,I meet FPGA.
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Participant
Posts: 35
Registered: ‎03-15-2012

Re: distributed RAM: timing errror on read

hi,

 

thanks for our answer.

 

It sounds, it is enought to constraint (FROM:TO) the 2nd path (DRAM -> capture register), which would be great. But how can i be sure, that the PERIOD constraint of the 1st path isn't overwritten partially (between DRAM and capture register)?