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Registered: ‎10-08-2009

downsampling with phase aligned clocks


I have a 100 Mhz(sysclock) clock signal going to a PLL which then generates a 50 MHz(clk0) signal and a 100 Mhz(clk1) signal.


I then have a data stream on the clk1 domain going at 100 Mhz (say 1,2,3,4,5,etc.) that I want to clock into the 50Mhz clk0 domainl and get the stream 2,4,6,8, etc, (downsampling). Do I need any special constraints (multicycle constraint?) or is the constraint for the sysclock sufficient.


How about in the opposite case. I have a data stream of (1,2,3,4,etc) on the 50 Mhz clock domain and I want to clock it into the 100Mhz clock domain and get the stream (1,1,2,2,3,3,4,4 etc..).


What timing constraints do I need?





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Xilinx Employee
Xilinx Employee
Registered: ‎05-07-2015

HI @luis.munoz


As your use case is to up samle / down sampling the data between two phase aligned clocks.
you would not need  to define multicycle contraints for this requirement.

As the bothe 50 Mhz and 100 Mhz clocks derievd from Same PLL.
Interclock analysis in both case will happen with a setup requirement  of 10 ns and Hod requirement of 0 ns.
Defining a clock on the PLL input clk(sysclock) would suffice.

Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
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