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Anonymous
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external feedback path for DCMs

Hi Everybody,

 

i'm trying to get my feedback clock for DCM off chip and back again for certain purposes. 

And, I want to see the results in timing analyzer. First, i tried it single ended, connected signals

and pins etc, supplied following constraint as it requested by the tool: 

 

NET "CLKFBP_I"     FEEDBACK = 100 ps NET "CLKFBP_O";

 

this worked perfect. I can see the results in timing anayzer as well. 

 

But, in second step, i wanted to use differential signals for clock feedback.

 

All i did was, adding OBUFDS and IBUFDS buffers to design and specifed signal standard  LVDS_25.

 

But now , software complains that the loop incomplete is and i don't see any deskew effect of DCM of course. 

 

In differential case my constraint looks like: 

 

NET "CLKFBP_I"     FEEDBACK = 100 ps NET "CLKFBP_O"; 

NET "CLKFBN_I"     FEEDBACK = 100 ps NET "CLKFBN_O"; 

 

or

 

NET "CLKFB*_I"     FEEDBACK = 100 ps NET "CLKFB*_O"; 

 

in both case no success.

 

Quick check in constraints guide:

 

"The basic UCF syntax is:
NET feedback_signal FEEDBACK =value units NEToutput_signal;
where
• feedback_signal is the name of the input pad net used as the feedback to the DCM
• value is the board trace delay calculated or measured by you
• units is either ns or ps. The default is ns.
• output_signal is the name of the output pad net driven by the DCM

 

FEEDBACK Propagation Rules
Both the feedback_signal and output_signal must correspond to pad nets. If attached to any
other net, an error results. The feedback_signal must be an input pad and output_signal must
be an output pad.

"

 

 

In my constraints net names are indeed the pad nets.

 

I don't know why in differential case feedback loop is not detected by the tool.

 

 

Has anyone also experienced something like this?

 

Thanks & 

 

 

 

 

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Anonymous
Not applicable
3,787 Views

Re: external feedback path for DCMs

Sorry, just to make it more complete:

 

input buffer is not IBUFDS, its IBUFGDS of course, being a GCLK pin. 

And, at output path, there is ODDR2 with D0,D1 connected to GND and VCC.

(output of the DDR  is same like CLock itself)

 

And, i used ISE 10.1.

 

 

 

 

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