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Observer
Observer
5,464 Views
Registered: ‎03-27-2008

fanout report

Hi,

 

   My question is if analysis tools from newer versions of ISE (8, 9 or 10.1) take into consideration the fanout of a signal when reporting delays (such as the Asynchronous Delay Report) or is the report based only on path-lengths?

   Are there any simulators which show a wave diagram of a high fanout signal after the design was placed and routed?

 

Thanks in advance,

Tamas

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Xilinx Employee
Xilinx Employee
5,462 Views
Registered: ‎01-03-2008

The timing analysis tool, TRCE, takes in to account all aspects of the net delay from source to each endpoint regardless of the release version. 

 

Modern FPGA architectures have buffered most portions of net-to-net connections, so RC delays caused by the number of loads has been minimized.

 

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