UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer tamasgy89
Observer
5,368 Views
Registered: ‎03-27-2008

fanout report

Hi,

 

   My question is if analysis tools from newer versions of ISE (8, 9 or 10.1) take into consideration the fanout of a signal when reporting delays (such as the Asynchronous Delay Report) or is the report based only on path-lengths?

   Are there any simulators which show a wave diagram of a high fanout signal after the design was placed and routed?

 

Thanks in advance,

Tamas

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
5,366 Views
Registered: ‎01-03-2008

Re: fanout report

The timing analysis tool, TRCE, takes in to account all aspects of the net delay from source to each endpoint regardless of the release version. 

 

Modern FPGA architectures have buffered most portions of net-to-net connections, so RC delays caused by the number of loads has been minimized.

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos