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alavala_suraj
Visitor
Visitor
582 Views
Registered: ‎08-25-2019

finding the values of tco, tsu, tsh

Hello,

          I am currently using SP701 EVALUATION KIT (xc7s100fgga676). i want to know in which manual can I find the values of tco, tsu and trce_delay for my board.

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

I believe report_datasheet command provides what you need.

Trace delay is already included in the report_datasheet results.

Trace delay of each pin is in the "Package pins" tab.

-vivian

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alavala_suraj
Visitor
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Registered: ‎08-25-2019

Hello Vivian,

Thanks for the help.

I could find the minimum and maximum trace delays under the "package pins tab".

However, I need tsu, th for outputs, but in the datasheet they have provided tco_max, tco_min values for the output.

And also, I need tco_min, tco_max values for input, they provided tsu, th for inputs.

So, I need help regarding this.

 

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

What is your purpose to have tsu and th for outputs, and tco for inputs?

 

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alavala_suraj
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Registered: ‎08-25-2019

The timings constraints wizard asks for the following value:

1. For the input ports (tco_max, tco_min)

2. For the output ports (tsu and th)

Without specifying these values,  I am getting these as critical warning when I perform the "Implementation Stage".

So, that is the reason I needed these values.

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

For inputs, tco is the timing of the thing thats driving the fpga input

  for outputs , Tsu / Th are the timings for the thing your driving, 

The tools use these timings to check the FPGA input and outputs meet the timings you circuit needs.

 

 

 

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viviany
Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎05-14-2008

Well, so what you need is to create the set_input_delay and set_output_delay constraints.

I take back my previous answers as I misunderstood your question.

 

You need to check the Datasheets of the device that is driving the FPGA input interface and the device that is receiving the output data from the FPGA.

-vivian

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alavala_suraj
Visitor
Visitor
309 Views
Registered: ‎08-25-2019

I have a doubt, I want to extend this question to an Mp Soc.

 

I have a project running on av net ultra-96 v2 which there is data is transmitted from PS side to PL side and vice-versa.

Specifically, data from my LPDDR4 is being transferred via AXI-lite.

So, in this case which system's datasheet should I consider? AXI-lite or LPDDR4.

Again after processing, the data is re-transmitted to LPDDR4 from PL side.

 

 

The second scenario,

I am currently using SP701 evaluation kit to verify my model on  pure fabric. So, I am just verifying it using ILA.

In this case, which one should I consider as driving system.

 

Sorry, If my questions sound trivial, but I need clarity to proceed.

Thank you.

 

 

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