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Observer alexrp92
Observer
227 Views
Registered: ‎07-16-2019

generate a clock

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Hi! I have a doubt about using the PL FABRIC CLOCK (fclk_clk0). it is set to 50 MHz, I need a 125 MHz clock for other IP, can I add a clocking wizard IP, top convert the 50 MHz signal to a 125 MHz? it is possible or that IP only can obtain lower freq values in the output?

If it is not possible, how can I obtain another clock signal?, can I create a 2second fclk_clk1 clock ?

Thanks! 

Imagen1.pngImagen2.png

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1 Solution

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Scholar drjohnsmith
Scholar
157 Views
Registered: ‎07-09-2009

Re: generate a clock

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when you want two clocks that are phase aligned , you have two choices,

a) use two outputs of the MMCM,

b) genrate one higher frequency clock, and use enables at the clock rate you want.

 

b) is easier , especialy if your new to this,

     you only have one clock to constrain around the design,

 

a) is a bit more interesting, it gives lower power, so for BIG ultrascale stuff it cna make a big difference to power, but constraining can be more interesting and as such liable to be wrong.

I can't see th eorriginal post whilst typing this and cant rember what your frequencies were .

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar watari
Scholar
223 Views
Registered: ‎06-16-2013

Re: generate a clock

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Hi @alexrp92 

 

I suggest you to turn on FCLK_CLK1 as 125[MHz], if you don't need synchronous between FCLK_CLK0 and FCLK_CLK1.

 

Best regards,

 

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Observer alexrp92
Observer
213 Views
Registered: ‎07-16-2019

Re: generate a clock

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Thanks! but do you know if the first configuration is correct? can I obtain a 125 MHz signal from 50 MHz with A CLOCK WIZARD IP?

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Scholar watari
Scholar
210 Views
Registered: ‎06-16-2013

Re: generate a clock

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Hi @alexrp92 

 

Did you configure PLL to generate 125MHz in Clock Wizard ?

If yes, it's correct behaviour.

 

Best regards,

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Observer alexrp92
Observer
194 Views
Registered: ‎07-16-2019

Re: generate a clock

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No, i had MMCM, I've just run the implementation ot the same configuration with the PPL primitive, it shows this error:

  • [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal system_i/clk_wiz_inicial/inst/clk_in1 on the system_i/clk_wiz_inicial/inst/plle2_adv_inst/CLKIN1 pin of system_i/clk_wiz_inicial/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

Do you know how to solve it?

 

thanks!!

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Scholar watari
Scholar
187 Views
Registered: ‎06-16-2013

Re: generate a clock

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Hi @alexrp92 

 

"DRC" means "design rule check" and Vivado prohibit cascade connection without like BUFG.

So, in this case, if you add BUFG before clock wizard module, you can resolve it.

 

However, I suggest you to use FCLK_CLK1, even if you can measure 125MHz after PLLE2_ADV.

 

Best regards,

 

Best regards,

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Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎05-22-2018

Re: generate a clock

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Scholar drjohnsmith
Scholar
158 Views
Registered: ‎07-09-2009

Re: generate a clock

Jump to solution

when you want two clocks that are phase aligned , you have two choices,

a) use two outputs of the MMCM,

b) genrate one higher frequency clock, and use enables at the clock rate you want.

 

b) is easier , especialy if your new to this,

     you only have one clock to constrain around the design,

 

a) is a bit more interesting, it gives lower power, so for BIG ultrascale stuff it cna make a big difference to power, but constraining can be more interesting and as such liable to be wrong.

I can't see th eorriginal post whilst typing this and cant rember what your frequencies were .

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos