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rex_nyu
Visitor
Visitor
6,687 Views
Registered: ‎08-12-2011

hold time violation during FPGA post place and route simulation in modelsim

I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below:

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 25 ns HIGH 50%;

My design does not have any errors in static timing analysis report after place and route. Part of the report is shown below:

Timing errors: 0  Score: 0

Constraints cover 191219 paths, 0 nets, and 38438 connections

Design statistics:
   Minimum period:   9.954ns{1}   (Maximum frequency: 100.462MHz)

However, when I run a post place and route timing simulation in modelsim. It gives me this error and the design does not generate the proper result in the simulation.

# ** Error: /home/rex/opt/Xilinx/10.1/ISE/verilog/mti_se/simprims_ver/simprims_ver_source.v(121020): $hold( posedge CLK:650974 ps, negedge I &&& (in_clk_enable1 != 0):651125 ps, 153 ps );
#    Time: 651125 ps  Iteration: 0  Instance: /tb/aes_wrapper_0/\aes_fwd_0/aes_fwd_core_inst/CIPHER_RND_1_ARK_ROW_1_4_ARK_COL_1_3_xor_itm_1_sg1 
# ** Error: /home/rex/opt/Xilinx/10.1/ISE/verilog/mti_se/simprims_ver/simprims_ver_source.v(121020): $hold( posedge CLK:650974 ps, negedge I &&& (in_clk_enable1 != 0):651125 ps, 153 ps );
#    Time: 651125 ps  Iteration: 0  Instance: /tb/aes_wrapper_0/\aes_fwd_0/aes_fwd_core_inst/CIPHER_RND_1_ARK_ROW_1_4_ARK_COL_1_2_xor_itm_1_sg3_0 
# ** Error: /home/rex/opt/Xilinx/10.1/ISE/verilog/mti_se/simprims_ver/simprims_ver_source.v(121020): $hold( posedge CLK:650974 ps, negedge I &&& (in_clk_enable1 != 0):651125 ps, 153 ps );
#    Time: 651125 ps  Iteration: 0  Instance: /tb/aes_wrapper_0/\aes_fwd_0/aes_fwd_core_inst/CIPHER_RND_1_ARK_ROW_1_4_ARK_COL_1_3_xor_itm_1_sg3_0 
# ** Error: /home/rex/opt/Xilinx/10.1/ISE/verilog/mti_se/simprims_ver/simprims_ver_source.v(121019): $hold( posedge CLK:650974 ps, posedge I &&& (in_clk_enable1 != 0):651125 ps, 153 ps );
#    Time: 651125 ps  Iteration: 0  Instance: /tb/aes_wrapper_0/\aes_fwd_0/aes_fwd_core_inst/CIPHER_RND_1_ARK_ROW_1_4_ARK_COL_1_2_xor_itm_1_sg3_2 
# ** Error: /home/rex/opt/Xilinx/10.1/ISE/verilog/mti_se/simprims_ver/simprims_ver_source.v(121020): $hold( posedge CLK:650974 ps, negedge I &&& (in_clk_enable1 != 0):651125 ps, 153 ps );
#    Time: 651125 ps  Iteration: 0  Instance: /tb/aes_wrapper_0/\aes_fwd_0/aes_fwd_core_inst/CIPHER_RND_1_ARK_ROW_1_4_ARK_COL_1_3_xor_itm_3 

I only know this is a hold time violation. How do I interpret this error information more precisely? How to solve this problem?

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1 Reply
vemulad
Xilinx Employee
Xilinx Employee
6,667 Views
Registered: ‎09-20-2012

Hi,

 

I hope this article may help you http://www.xilinx.com/support/answers/5255.htm

 

It contains the details about why the setup/hold violations occur in timing simulation and how to overcome them.

 

Thanks,

Deepika.

Thanks,
Deepika.
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