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Visitor hotak321
Visitor
522 Views
Registered: ‎10-19-2018

how much is delay time of bufio gate in zynq z7-20 ?

 I want to use bufio delay time  to use (* io_buffer_type ="bufio" *).

How much is time bufio delay time ?

Can I increase bufio delay time ?

if not so, I want to use another more sufficient delay time of other gate ?

Could you recommend it?

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17 Replies
Moderator
Moderator
482 Views
Registered: ‎03-16-2017

Re: how much is delay time of bufio gate in zynq z7-20 ?

Hi @hotak321 , 

Check https://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf for BUFIO delay values. Table-68.

I don't think so you can vary the primitive delay. 

Check other buffer's delays in that data sheet.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Visitor hotak
Visitor
464 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

Thanks a lot.

Can I ask a question of cascased bufio dely synthesis?

I want to have cascaded flipflops with bufos?

Can they be synthesized and implemented?

I want to have more flipflop output delay times because I want to have more hold time.

If so, how can I get more hold time? 

Could you recommend it?

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449 Views
Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

As shown in Table 1-1 of UG472, BUFIO can connect to components found in OLOGIC or ILOGIC blocks of the Zynq7.  Page 134 of UG471 (v1.10) shows that the ODELAY component is found in the output block of HP banks and can be inserted after OLOGIC to delay data being sent out of the FPGA.  Page 480 of UG953 (v2019.1) shows how to instantiate ODELAY into your design.

To delay a clock that is being sent out of the FPGA, we typically use the phase-shift feature of the MMCM and a "set_property PHASESHIFT_MODE LATENCY" constraint for the MMCM.

Mark

Visitor hotak
Visitor
420 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

I want to have cascaded flipflops with obuf with some delay time.

Could they be synthesized and  implmented ? (I think that obuf logics bewteen input ports and outputs of submodules should not  be removed)

 

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392 Views
Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

It sounds like you are trying to use BUFIO and to create source-synchronous output from the FPGA (ie. you are trying to send both a clock and data out of the FPGA)?  If so, they we normally do this as shown in the schematic below.
BUFIO_SSO.jpg

   I want to have cascaded flipflops with obuf with some delay time.  
   I want to have more flipflop output delay times because I want to have more hold time.
You can cascade more flip-flops to the left of DATO_reg.  However, each flip-flop will add a full clock-cycle of delay, which will not help you control hold time.  However, you can insert ODELAY between DATO_reg and DATO_OBUF_inst to control hold time by less than a full clock-cycle.

Note also from the schematic that the ODDR is used to forward the clock - which is a preferred method.  You should not forward the clock by directly connecting the output of BUFIO to a pin/port of the FPGA. 

Also note on the ODDR that I have set (D1=0 and D2=1), which should help with timing analysis compared to (D1=1 and D2=0).

Mark

Visitor hotak
Visitor
387 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

I want to FDRE with obuf to be connected with FDRE with obuf  not to be above picture.

As a such, several serial FDRE with obuf should be connected with FDRE with obuf. 

Is it impossible , now?

 

I want to add obuf at the position of yellow net wire region.

1.JPG
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373 Views
Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

    I want to add obuf at the position of yellow net wire region.
If your FDRE labelled U1 and U2 are located in the FPGA fabric (and not locked in the IOB) then you can connect an OBUF to their outputs (the yellow wires).

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Historian
Historian
327 Views
Registered: ‎01-23-2009

Re: how much is delay time of bufio gate in zynq z7-20 ?

If your FDRE labelled U1 and U2 are located in the FPGA fabric (and not locked in the IOB) then you can connect an OBUF to their outputs (the yellow wires).

I don't think that's true.

The .O of the OBUF is connected only to the bond site of an FPGA pin - it cannot connect to an internal net. Its main (almost sole) role is to bring a signal out of the FPGA. Of course, it is possible to go out the OBUF and back in through the IBUF of the same pin (and get back to the fabric), but the signal literally goes through the pin of the FPGA onto the board. This "internal to internal" connection is affected by the external pin - if the pin has a large trace capacitance on it, then it will affect the delay of this path. If the pin is tied to ground, then the path will be broken (and always return 0).

Avrum

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Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

I understood you wanted to add two more OBUF to your circuit schematic  - and .I pin of each new OBUF connects to a yellow wire.  -and .O pin of each new OBUF connects to a separate pin/port of FPGA.   Yes?

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Visitor hotak
Visitor
305 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

Yes, I want to more serial flipflops same as above.

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296 Views
Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

Is this what you want?

OUT_123.jpg

    OUT1 <= reg1;
    OUT2 <= reg2;
    OUT3 <= reg3;
-- P0: process(clk1) begin if rising_edge(clk1) then reg1 <= IN1; reg2 <= reg1; reg3 <= reg2; end if; end process P0;
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Highlighted
Visitor hotak
Visitor
287 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

// No, as my intention code as follows. if impossibe with intenal flipflop with buf, I want to have master slave flip flop instead of flipflop with buf.

module dff_bo

(
output q3,
// output q1,q2,q3,
// (* clock_buffer_type ="bufg" *)
input clk,
input d
);
wire q1,q2;
wire q1w,q2w;
dff_0 U1 (q1,clk,d);
buf G1 (q1w,q1);
dff_b U2 (q2,clk,q1w);
buf G2 (q2w,q2);
dff_b U3 (q3,clk,q2w);

endmodule

module dff_b

(
output reg q,
/* input clk,
input d
*/
input clk,
(* io_buffer_type ="bufio" *)
input d

);


always@(posedge clk)
q = d;
endmodule

module dff_0

(
output reg q,
input clk,
input d
);


always@(posedge clk)
q = d;
endmodule

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275 Views
Registered: ‎01-22-2015

Re: how much is delay time of bufio gate in zynq z7-20 ?

@hotak 

Please draw a picture of what you want.  I am not familiar with Verilog.

 

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Visitor hotak
Visitor
236 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

I see, I attached schematic with yellow region.

yello positon is inserted with buf gate to be connected with flipflp input pin.

 

1.JPG
2.JPG
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Historian
Historian
253 Views
Registered: ‎01-23-2009

Re: how much is delay time of bufio gate in zynq z7-20 ?

It is very hard for us to answer your questions, since they make no sense.

WHY would you want to have buffers between flip-flops? There is no reason for that. Synchronous design allows for any amount of combinatorial delay between flip-flops as long as the delay doesn't exceed the clock period (with some other factors). Other than that, the number of them (or there existance) only matters for functional purposes - buffers have no "function".

Second, there is no concept of "regular" buffers in an FPGA. All existing buffers have specific purposes

  • BUFIO, BUFR, BUFH, BUFG are only clock buffers - they can only drive the roots of their respective dedicated clock trees
  • OBUF, IBUF, OBUFT, IOBUF are IO buffers - one side of them can only drive/receive from the physical pin of the FPGA (and nothing else)

None of these can be used for anything other than their intended purpose. Furthermore, there is no need for "regular" buffers in the FPGA array - the entire FPGA interconnect is essentially buffers - as a signal is routed from one CLB to another it goes through one or more fully buffered switch interconnect matricies.

Furthermore, your Verilog is basically nonsense - things named DFF are not actually DFFs and have incomplete port lists. Your coding structure for DFFs is not recommended since you use blocking assignments instead of non-blocking assignment. I have no idea what you are trying to do with your clock_buffer_type directive...

So what are you trying to accomplish - it is impossible for us to answer your verys specific implementation questions when we have no idea what you are trying to accomplish.

Avrum

Visitor hotak
Visitor
242 Views
Registered: ‎06-13-2018

Re: how much is delay time of bufio gate in zynq z7-20 ?

thank you for your kind explanations.

Though Interconnect switch acts like buffer with delays, can they support clock skew problem for example many stages of shift register?

I think that clock skew problem or hold time to be supported is solved via master slave flipflop ( with internal dual edge clock) or buffer with some delay time.

and I think that  buffer have to have function to have driver strength, driver fanout , have some delay time in some case, others buffer have to have zero delay time.

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Historian
Historian
228 Views
Registered: ‎01-23-2009

Re: how much is delay time of bufio gate in zynq z7-20 ?

Though Interconnect switch acts like buffer with delays, can they support clock skew problem for example many stages of shift register?

You are way way way overthinking things here.

While what you say is true (clock skew can cause hold problems on things like shift registers) these are all dealt with by modern design styles and the implementation tools - you don't have to worry about them.

Solutions like using master/slave latches (or really two phase non-overlapping clocks) haven't been used in decades, and manually fixing them with the insertion of buffers is also a thing of the distant past.

First, clock skew is minimized in all digital flows. In ASIC designs, the clock insertion tool minimizes skew as it builds the clock trees. In FPGAs there are dedicated, pre-implemented clock networks in the device that are designed to have low skew. In most cases (at least in FPGA), the low clock skew combined with the relatively long clock-to-output time of the flip-flops and the relatively long routing delay (even between pairs of flip-flops) is enough to ensure that there are no hold time violations.

But even if there are hold time violations, all the tools are timing driven. Assuming your design is constrained (and they absolutely must be) then the tools understand the clocks including the clock skew. When it comes time for routing (after placement) the tools check for hold time violations, and if any are found, they automatically fix them by inserting extra routing delay. Again - this is all handled automatically.

So, you (the designer) simply don't have to worry about this.

and I think that  buffer have to have function to have driver strength, driver fanout , have some delay time in some case, others buffer have to have zero delay time.

These too are concepts that just don't exist in an FPGA.
 
The routing network is fully buffered - every node of an interconnect drives a fixed amount of load - therefore there is no concept of "driver fanout" or "driver strength" in an FPGA.
 
As I mentioned above, you never need to insert delay with a buffer in an internal path. On external paths (I/O) there are other things for inserting delay (IDELAY/ODELAY, clocks with phase shifts) - you never implement these delays with buffers (or other cells) - at least in normal synchronous design styles.  (I am not including academic work that attempt to do time domain processing).
 
So, for all these reasons, there are no "regular" buffers in an FPGA - you just don't need them.

Avrum