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Highlighted
10,930 Views
Registered: ‎02-01-2009

how the 32 bit output can be synchronized.?

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i am implementing algorithm in vhdl using ise webpack 10.1 aqnd simulating on Modelsim , which requires 32 bit input and 32 bit output
but output varies for 132 ps and then stables down. as all 32 bits at a time do not changes state so the glitches come in output .

so i am attaching image please do suggest me how to overcome this problem. i am using vertex II pro device. also tested same in spartan3e device gives glitched output for 1.8ns

or it is a device limitation? or anything else?

 

output_register: register32 port map(
clk => clk,
rstn => rstn,
Input => ctOutReg,
output => ctOut
);

-- register port map

entity register32 is
port(clk,rstn : in std_logic;
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end register32;

architecture Behavioral of register32 is
begin
process(clk,rstn)
begin
if (rstn='1') then
output <= x"00000000";
elsif (clk'event and clk='1') then
output <= input;
end if;
end process;
end Behavioral;

 

 

as shown i used the register of 32 bit.

 

 

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Xilinx Employee
Xilinx Employee
13,064 Views
Registered: ‎08-13-2007

You still didn't mention if this is a functional or back-annotated timing simulation and if this is the entire design.

 

Different routing delays from the register stages to the output pads could explain this. If you've implemented the design, you should also check the map report (mrp) to see if the input and output register stages are packed into the IOBs. But if this is the entire design, they can't be and the peripheral timing will change from implementation run to run.

 

bt

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Observer
Observer
10,914 Views
Registered: ‎03-31-2009

Check your timing report.  It will probably show the 132pS of timing variation you are experiencing.  Maybe you can put timing constraints on your signals so they all come out at 140pS or something like that.  I haven't done any asynchronous design but it looks interesting!  I may have an application coming soon so please post your fix when you get this figured out. 

 

John D

 

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Xilinx Employee
Xilinx Employee
10,901 Views
Registered: ‎08-13-2007

Your picture didn't come through so it isn't clear from you mean by "glitches come in output"

Are you doing a functional or back-annotated timing simulation?

If this is your entire design, consider that an ideal FPGA design would register all of the inputs and all of the outputs in the IOB registers. Otherwise routing delays to the fabric will effect your peripheral timing.

 

bt

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Highlighted
10,895 Views
Registered: ‎02-01-2009

 Please can any body help me and tell how to uplaod image which is on your local drive

as per options available it asks for url of image location so please do help me

?

?

 

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Xilinx Employee
Xilinx Employee
10,899 Views
Registered: ‎08-13-2007
 
temp.JPG
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Highlighted
10,883 Views
Registered: ‎02-01-2009
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Highlighted
Xilinx Employee
Xilinx Employee
13,065 Views
Registered: ‎08-13-2007

You still didn't mention if this is a functional or back-annotated timing simulation and if this is the entire design.

 

Different routing delays from the register stages to the output pads could explain this. If you've implemented the design, you should also check the map report (mrp) to see if the input and output register stages are packed into the IOBs. But if this is the entire design, they can't be and the peripheral timing will change from implementation run to run.

 

bt

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Highlighted
10,839 Views
Registered: ‎02-01-2009

yes this is complete design output and simualtion is back-annotated timing simulation.

and also i tried to place the ctout<0:31> in IOB using PACE it has given me improvement in the glitch part for device spartan 3e 1600 fg320 -4 as from 1.8 ns to 1.0 ns so improvement of 800 ps.

so plase do suggest how to minimze the same further with some techniques.

 

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