Hello, I'm new to using FPGAs. I currently have the ISE 10.1 suite installed including System Generator, as well as the full Matlab/Simulink Suite. I'm trying to build a simple design for a Virtex 2P DSP fpga.
Basically, I'm trying to figure out what the latency per block is. I don't know how to figure that out. Is there any way that you can verify what latency you need so you can properly add your delays lines?
The simulink model worked fine with desired results, but the corresponding XSG model always give me internal error of different blocks. when I vary the latency, some other block will give the same internal error .