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mgdudhat
Contributor
Contributor
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Registered: ‎09-15-2019

how to fix : Inter-Clock path - setup time error- TNS, WNS error (Negative Value)

Hi all,

i am trying to generate the bit stream for the Artix-7 based Project in order to measure the throuput measurement using axi qspi core during read/write process to external qspi micron flash, but after implimentation stage i have noticed that it shows me following timing summary result as attached (WNS : -0,245 ns, TNS: -0,245 ns, one endpoint failed ). So  i have understood that my design has failed due to this timings constraints error and i am trying to find the right solution for this. 

Actually the path showed for this failure is between cs pin (SPI_Flash_ss_o)  of axi qspi core to the Input pin (qspi_ss_o) of sram based shift Register which i used to connect the cs Signal to the axi timer in capture mode. In fact, I am a bit newbi for this kind of inter Clock paths issue. One Question: If i would  ignore this at the moment, then would i get the expected behaviour on hardware.?

Have i done any mistake in this then, please let me know your suggestions or advices. Thank you.

timing_summry.PNG
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10 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
1,582 Views
Registered: ‎05-22-2018

Hi @mgdudhat ,

In Timing report, the Datapath Delay row is showing that net delay is contributing 94.394%, it should be within 50%.

So i guess working on the net delay will help in closing timing. please check page no.6 and 7 of below linK:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1292-ultrafast-timing-closure-quick-reference.pdf

Thanks,

Raj

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mgdudhat
Contributor
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Registered: ‎09-15-2019

Hi @ rshekhaw,

thanks for the Reply. actually i read that pdf a bit. In fact i used the following constarints in .xdc file and then i have found no negative values but i am not sure that whether this is Right solution to avoid these WNS, TNS Violation. 

Used TIMINGS Constraints:

set_false_path -from  [ get_clocks clk_sck ]    -to [ get_clocks clk_pll_i ]

set_false_path -from [ get_clocks  clk_pll_i ]     -to [ get_clocks clk_sck ]

Question : If i ignore These values using following "set_false_path"  constarints then would it affect to the Hardware design functionalites or would malfunction it.?

Let me know your opinion about these. Thank you.

 

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pedro_uno
Advisor
Advisor
1,534 Views
Registered: ‎02-12-2013

I would agree that is probably a false path. De-constraining false paths is a big part of getting a design into production. What you are doing is probably just fine but in my design I don't like to use overly broad set_false_path commands. Those you show can cover up a lot of accidental clock crossing paths that might need to be examined. I like to use a set_max_delay command between specific endpoints rather than ignoring all paths between two clocks as you have done. Here is an example:

set_max_delay -from [get_pins capture_ram_inst/sr_reg/C] -to [get_pins {axi_regfile_inst/axi_rdata_reg[4]/D}] 20.1

The delay constraint of 20.1 is chosen to be easy to meet but provides some kind of limit. Also, using a unique number like 20.1 makes the constraint identifiable in your timing report.
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avrumw
Expert
Expert
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Registered: ‎01-23-2009

I think we need to be very careful here.

It is pretty clear that this is a clock domain crossing path. So something needs to be done about it. But as to what depends greatly on what this path is, and why it is showing up as a violation. I can think of three possibilities.

The first is that it is an unintentional clock domain crossing path. Somewhere in this design, two portions of the design that are supposed to be (or are assumed to be) running on the same clock are being driven by different clocks. In other words, this is supposed to be a synchronous path, but because the clocks are not connected properly, ends up being a clock domain crossing path. In which case, the solution is to fix the RTL/block design.

The second is that it is a "bad" clock domain crossing. These two modules are supposed to be clocked by different domains, and there is a need to bring data between them. If this is the case, then a proper clock domain crossing circuit (CDCC) is necessary. If one doesn't already exist (i.e. this path is already part of a CDCC - see below), then a proper CDCC appropriate for this clock domain crossing must be coded and constrained.

The third possibility is that this is already part of a CDCC - it is impossible for me to tell from this report. A proper CDCC is only complete with an "appropriate" timing exception; the correct exception depends on the nature of the data being crossed and the construction of the CDCC. What worries me is, if this path is part of an IP, then this CDCC should already be part of the design, including having the appropriate constraint. Since the path doesn't already have an exception, this is probably not the case... 

Given these three possibilities, simply adding the exception is unlikely (but possible) to be the correct solution; the system needs to be properly analyzed to figure out what the path is, and which of the above situations best describes the problem. 

In any event, I agree with @pedro_uno - you shouldn't apply "blanket" clock-to-clock set_false_path commands; they are inherently dangerous. A more tightly controlled exception (like the one @pedro_uno showed) is more appropriate (assuming, again, that simply adding an exception is the right course of action).

Avrum

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mgdudhat
Contributor
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Registered: ‎09-15-2019

Hi @pedro_uno,

i thank you for the Reply. I would like to ask you  for the "set_max_delay" constraint as i want to use this constraint compared to "set_false_path" onwards in order to be in safe and reliable zone. Could you tell me how to find /set the set_max_delay in my design issue (like in your case you have decided 20.1 ns) from the schematic /Reports above provided. 

Many thanks.

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pedro_uno
Advisor
Advisor
1,380 Views
Registered: ‎02-12-2013

Hello,

I think you are asking how I got the very specific set_max_delay command syntax.  There is a trick.

I attach a couple of screen shots.  When I want to analyze my timing paths I open the project in Vivado and open the implemented design.  Then I run the report timing summary which then lists my worst paths for any kind of clock combination.  The first screen shot shows a list of paths. You can right click on one of the paths and select set max delay -> start point to end point. It brings up a menu shown in the second screen shot. At the bottom the tcl command is shown in clear text.  You can copy and paste that into your constraints file. 

Often, many of the missing paths are really the same thing. You can replace the specific numbers in the command with wild cards to cover an entire class of path in one command.

Finally, what avrum said above is good advice.  It is important to understand any signals that cross clock domains and make sure you are doing the right thing.

Good luck.

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Screenshot from 2020-06-01 15-25-59.png
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mgdudhat
Contributor
Contributor
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Registered: ‎09-15-2019

Hi thanks again to you and avrum too. Actaully I did the steps as you shown above but i m getting zero value delay as shown below, i am not sure whether ist true or not: 

Generated Timing constarint:

set_max_delay -from [get_ports {SPI_Flash_ss_io[0]}] -to [get_pins {design_1_i/c_shift_ram_0/U0/i_synth/i_bb_inst/gen_output_regs.output_regs/i_no_async_controls.output_reg[1]/D}] 0.0

Actually i changed the above microblaze block diagram design due to "microblaze held in reset" error. so i have bit change in negative values as attached. Let me know your suggetion. Thank you all.

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pedro_uno
Advisor
Advisor
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Registered: ‎02-12-2013

I have to say that this cannot be a simple case of clock crossing. Your violation is over 5 microseconds. It is on a spi interface which can be very slow but you have something else fundamental wrong.

Can you find a working example design and hack it to fit your needs? That is a good way to get back on the right path. Good luck.
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mgdudhat
Contributor
Contributor
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Registered: ‎09-15-2019

Hey @pedro_uno,

thanks a lot. Actually again I optimized the top level block diagram (it was related to the ext_rst which was fed to both processor resert module and mig module too, after connecting it only to the mig module and then generated reset from the mig connecting to the processor reset module, after implimantation the WNS and TNS value was again reduced to less than one as shown attached) so reduced the WNS, TNS again less than 1 ns value as it was at the begining. 

Now could you please let me know how to set or rougly estimate the maximum delay value as u set it to 20.1 ns in your case. In my case i again followed the steps you already shown and but got the  following zero value maximim delay constraint from the Vivado tool which i copied it to .xdc file:

#set_max_delay -from [get_pins {design_1_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I/SS_O_reg[0]/C}] -to [get_pins {design_1_i/c_shift_ram_0/U0/i_synth/i_bb_inst/gen_output_regs.output_regs/i_no_async_controls.output_reg[1]/D}] 0.0

Thank you so much for your support in advance.

timing_constraint_WNS_TNS_negeative.PNG
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pedro_uno
Advisor
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Registered: ‎02-12-2013

That number on the end is the max delay requirement.  The GUI tool puts 0.0 in there by default.  You are supposed to edit it to be something reasonable.

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