how to know the total time it takes to execute the code?
i have my two VHDL encryption algorithms, and i need to know the total time elapsed for encrypt for both of them in order to know which one has less delay. How i can measure the delay or total time elapsed in Vivado?
This is easily measured in a VHDL testbench. You can count clock cycles with a counter, and determine the run time in terms of clock cycles. This is the usual metric.
Another metric which is relevant for FPGA designs is the Fmax of the design, which plainly stated is: How fast can you run the clock? This takes synthesis, timing constraints, and place & route benchmarking. Highly pipelined designs can run MUCH faster than designs without pipelining, so this is an important design consideration.
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