10-21-2019 11:07 AM
I am having problem with long carry8 chain,
Due to which design fails in timing when clock freq is 500mhz.
Can someone please suggest any workaround.
RTL for problem.
reg [255:0] hash;
reg[255:0] target
If(hash <= target)
valid_nonce <= 1;
else
valid_nonce <= 0;
I have attached screenshot
Thanks and regards
10-21-2019 12:08 PM - edited 10-21-2019 12:11 PM
Some suggestions:
1. Use the FewerCarryChains synthesis directive, or set the CARRY_REMAP property on the cells to be removed by opt_design.
2. Add pipelining registers to reduce logic levels.
3. Run report QoR suggestions in Vivado GUI and observe the suggestions and apply accordingly. Check UG906 (page 154 onwards) for more info. on it. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug906-vivado-design-analysis.pdf