11-25-2018 11:51 AM
I am getting hold violation due to clock skew. this skew is due to gated clock. pls help me on this.
NOTE : any help or suggestions are highly appreciated.
11-25-2018 01:36 PM
Avoid using that structure for gated clocks. Instead, use a synchronous clock enable on the destination FFs (preferred) or use a BUFGCE to gate the clock making sure to account for it in static timing analysis. The hold violations you're seeing are known using combinatorial clock gating.
Give kudos if helpful. Accept as solution if it solves your problem.
11-25-2018 04:49 PM
I agree with patocarr’s recommendations for gating a clock.
By routing a clock through a LUT, you are doing is called “pulling a clock from the clock-tree” or “routing a clock through the FPGA fabric”. This usually causes large clock-skew and problems with timing analysis. Generally, you want clocks to be routed only to the following:
Here are other situations where you might want to “pull a clock from the clock-tree” - and what you should do instead: