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Registered: ‎10-12-2016

how to overcome hold violation due to skew ?

Hi Friends, 

I am getting hold violation due to clock skew. this skew is due to gated clock. pls help me on this.



NOTE : any help or suggestions are highly appreciated. 

Thank You 

S Sampath 

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2 Replies
Registered: ‎01-28-2008


  Avoid using that structure for gated clocks. Instead, use a synchronous clock enable on the destination FFs (preferred) or use a BUFGCE to gate the clock making sure to account for it in static timing analysis. The hold violations you're seeing are known using combinatorial clock gating.




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Registered: ‎01-22-2015


I agree with patocarr’s recommendations for gating a clock.

By routing a clock through a LUT, you are doing is called “pulling a clock from the clock-tree” or “routing a clock through the FPGA fabric”.  This usually causes large clock-skew and problems with timing analysis. Generally, you want clocks to be routed only to the following:

  • clock-management-tiles (eg. MMCM or PLL)
  • clock buffers (eg. BUFG, BUFGCE)
  • the clock-pins of digital components (eg. C-pin of a register)

Here are other situations where you might want to “pull a clock from the clock-tree” - and what you should do instead:

  • Sending a clock out an FPGA pin/port: DON’T simply connect the clock to the port. DO use the ODDR (see Fig 3-7 in UG903)

  • Creating a really slow clock: It is usually best to have all clocks in your design be an output from an MMCM or PLL. However, the MMCM and PLL have a minimum output frequency (about 4.7MHz for MMCM and about 6.2 MHz for PLL). So, if clocks slower than these minimums are needed, then:  DON’T route the clock to a counter in the FPGA fabric and use the output of the counter as a clock. DO use a FPGA fabric counter to toggle the clock-enable pin of a BUFGCE or BUFHCE as shown in <this> post. You might also find the discussion of the “toggle” in <this> post to be helpful.