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Observer swseo83
Observer
482 Views
Registered: ‎05-23-2017

how to set min and max option of set_output_delay ?

How can we set min and max option of set_output_delay tcl command?

 

First, please take a look at the figure and the tcl command we wrote as below.

We would like to 2.5ns setup and 1ns hold time for the external device.

However, the post simulation result shows that there are over 8ns delays for all chip output of our FPGA.

 

set_output_delay -clock [get_clocks clk_usb] -max 2.500 [get_ports {{USB_ABUS[0]} {USB_ABUS[1]} USB_CSn USB_OEn USB_PKTEND USB_RDn USB_WRn}]
set_output_delay -clock [get_clocks clk_usb] -max 2.500 [get_ports {{USB_DBUS[0]} {USB_DBUS[1]} {USB_DBUS[2]} {USB_DBUS[3]} {USB_DBUS[4]} ....]

set_output_delay -clock [get_clocks clk_usb] -min 1.000 [get_ports {{USB_ABUS[0]} {USB_ABUS[1]} USB_CSn USB_OEn USB_PKTEND USB_RDn USB_WRn}]
set_output_delay -clock [get_clocks clk_usb] -min 1.000 [get_ports {{USB_DBUS[0]} {USB_DBUS[1]} {USB_DBUS[2]} {USB_DBUS[3]} {USB_DBUS[4]} ....]

 

Then, I delete the last two lines (-min option commands) as below, then it works properly.

set_output_delay -clock [get_clocks clk_usb] 2.500 [get_ports {{USB_ABUS[0]} {USB_ABUS[1]} USB_CSn USB_OEn USB_PKTEND USB_RDn USB_WRn}]
set_output_delay -clock [get_clocks clk_usb] 2.500 [get_ports {{USB_DBUS[0]} {USB_DBUS[1]} {USB_DBUS[2]} {USB_DBUS[3]} {USB_DBUS[4]} ....]

Interestingly, For both cases, there was no timing faults or errors between clk and clk_usb.

I do not know what is difference between them (using both min and max option , and using no option).

Please recommend some threads or documents to fully understand "set_output_delay".

I read most of threads in this forum, but the detailed information is not enough.

 

Please help us.

 

Thank you.

set_output_delay_min_q.jpg
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3 Replies
Explorer
Explorer
443 Views
Registered: ‎07-18-2018

Re: how to set min and max option of set_output_delay ?

Hi swseo83,

    Setting output delays just tells the tool how to modify the input or output static timing calculation. So if a downstream or upstream device is going to provide data centered around a clock edge, or aligned to an edge, or if the valid window is smaller then a full clock period due to that devices own setup and hold requirements, the timing engine can be informed and let you know if it can or cannot meet that requirement.

What it will not do, is change the delay of the signals.

It will just let you know if it meets or fails that requirement.

The tool will put effort into closing timing when you re-implement the design with those constraints, but usually if the requirement is dramatic, if will be the users responsibility to either add a phase shift between the clock and the data via something like a MMCM, or to add IO DELAYs to the paths to meet that requirement.

So when you set no option, vs the constraint, you won't see anything change in a simulation, but you can review the timing paths in the timing report to see how they are affected.

I would highly recommend using the wizard to write these constraints, as you can specific the delay requirements of the downstream device in terms that ideally match how that downstream device describes it's requirements in it's own datasheet(Makes it easier then trying to translate to a delay number yourself), and it will produce the right constraints to check for that.

I would start with page 157 of UG 949: https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2018_3/ug949-vivado-design-methodology.pdf#nameddest=TimingClosure

 

Observer swseo83
Observer
411 Views
Registered: ‎05-23-2017

Re: how to set min and max option of set_output_delay ?

Thank you very much for your kind answers.

I have realized that there was wrong option for set_output_delay. It should be negative value for -min option.

Now, I am facing a new problem.

Considering only the timing constraints of Setup Time, we defined constraints as follows:
set_input_delay -clock [get_clocks clk_usb] -max 7.500 [get_ports {{USB_DBUS[0]} {USB_DBUS[1]} {USB_DBUS[2]} ...]. Data is ready 7ns after the rising edge from an external device.
set_output_delay -clock [get_clocks clk_usb] -max 2.000 [get_ports {{USB_DBUS[0]} {USB_DBUS[1]} {USB_DBUS[2]} ...]
The period of the clock is 10ns.

The timing report shows that the design failed to meet the timing requirements for input port (source clock is clk_usb, and destination clock is clk).
-2.896ns slack occurs for input (failed the timing requirement), but total delay between input ports and the registers is just 1.441ns. (worst case)
4.391ns slack occurs for output (meet the timing requirement), we have the plenty of time for the outputs. (worst case)

Thus, we thought that if the phase of the clock "clk_usb" can be shifted 3ns, the slack would be 0.104ns for inputs and 1.391ns for outputs, which truly meet our design time requirement.
I expected Vivado to automatically shift the phase of the clock according to the timing constraints we have set, but is there something I need to set up more?

Could you please refer to the link http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface ?
The example is for ISE.
Thus, we have just re-written the codes and IPs to be compatible with Vivado.

We have been struggling for three weeks to solve this problem.
Please help us.
Thank you.

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Explorer
Explorer
329 Views
Registered: ‎07-18-2018

Re: how to set min and max option of set_output_delay ?

Thus, we thought that if the phase of the clock "clk_usb" can be shifted 3ns, the slack would be 0.104ns for inputs and 1.391ns for outputs, which truly meet our design time requirement.

I Think that seems like it would be a reasonable expectation.


I expected Vivado to automatically shift the phase of the clock according to the timing constraints we have set, but is there something I need to set up more?

Vivado will not do that for you. The best way to do this is to add a MMCM that produces a phase shifted forwarded clock. It's likely going to provide the best flexibility to address meeting timing.

It might also be possible to delay the clock or the data (depending what device family) to get enough to meet your requirement, but the MMCM/PLL is likely the better choice.

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