04-24-2018 02:34 AM - edited 04-24-2018 02:37 AM
I have a source synchronous interface goes to my FPGA. but the clk is go through a bufg, pll, bufgmux,..I'm confused
(main purpose is that the incoming clock is falling edge aligned with data, i need to shift 180 with pll to make it rise edge aligned. since other module in the FPGA is rise edge sampling, i don't like mix the neg edge and pos edge toghther which make problems...)
clk_in----ibufg-----|PLL|------clk_o1(phase shift 180, same frequency)-----|bufgmux|-------clk_o
| |------clk_o2(phase shift 0, same frequency)-----| |
I did get has suggest from https://www.xilinx.com/support/answers/59893.html
below is my draft
create_clock -period 10.172 [get_ports clk_in]
set_multicycle_path 2 -from [get_ports data_in]
set_input_delay -clock [get_clocks clk_in] -clcok_fall -max 4 -add_delay [get_ports data_in]
set_input_delay -clock [get_clocks clk_in] -clock_fall -min 3 -add_delay [get_ports data_in]
for source synchronous interface, clk and dat is length equal on layout, so the different is only reply on the transmit device.
is may edge align, or center align. how could we set max and min? unless we get real board measure?
04-24-2018 09:57 AM
We have two methods to determine the value used for the set_input_delay. One is to measure the board trace delays with the upstream clock-to-out delays to determine the values for min and max. The second method is to know the clock and data relationship of the interface. If the interface has a defined specification of 1ns setup and 1ns hold, then you can defined the values for min and max accordingly.
For more information on set_input_delay, I recommend reviewing UG903, page 98 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug903-vivado-using-constraints.pdf)
Please let me know if you have any other questions,
04-24-2018 06:28 PM
Thanks for heads up, I'll read ug903, but instead, can you please give me more information about the words below
I can understand your first method
but how to define the input delay parameter with the setup and hold request?
04-25-2018 10:02 AM
I recommend reviewing UG949 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug949-vivado-design-methodology.pdf), page 152.
The setup/hold requirements translates to -max for setup and -min for hold.