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4,967 Views
Registered: ‎08-30-2007

internal register to ouput pad data delay , how to decrease it?

 





 

for Backplane.twx, there is a timing error, 
TS_CLK0_OUT=PERIOD TIMEGRP "CLK0_OUT" TS_XGMII5_RXCLK HIGH 50%
this timing constraint is not the ones that I added manually, it is auto-generate, the XGMII5_RXCLK is global clk input signal, the CLK0_OUT is the XGMII5_RXCLK' DCM output pin,  the maximum delay is rand<29> (internal register)  to DATA_OUT<29>, whose value is 5.263 ns,  how to solve this problem, I need to manually to re-place the internal egister rand<29>, do not I ?

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Xilinx Employee
Xilinx Employee
4,610 Views
Registered: ‎08-10-2008

Re: internal register to ouput pad data delay , how to decrease it?

Can you please paste the timing error path into this page?
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