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Observer linwei8
Registered: ‎11-08-2016

issues with different timing in synthesis and implementation

1. I am wondering why the timing is different in synthesis and implementation, and do we need to fixed the timing error in synthesis?






2. I am wondering why some of timing constraints failed to take effect in synthesis but correctly applied to implementation.

For example, one of my constraints in line 300 is "set set_false_path -through [get_nets dut/rx_aresetn]".

They both applied to syn and imp, since i can find them when i open "Edit Timing Constraint" (in both syn and imp tab), but there is an warning in syn says "[Synth 8-3321] set_false_path : Empty through list for constraint at line 300 of proj_v1_wrapper.xdc.".

I didn't find the same warning in the imp, and the the net "dut/rx_aresetn" can both be found in syn and imp.


3. IPs is locked.

There is an warning says "One or more IPs have been locked in the design 'proj_v1.bd'. Please run report_ip_status ". I tried to report the ip, but the result is all ip is up-to-date and no missing file is delected.  How can i solve the problem. I am currently using vivado 2017.1.

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2 Replies
Teacher muzaffer
Registered: ‎03-31-2012

Re: issues with different timing in synthesis and implementation

@linwei8 synthesis timing is only an estimate but implementation timing values are real so you certainly need to close implementation timing but you can use synthesis timing as a guideline. If it's below a couple hundred ps, it's OK to proceed to implementation but too large synthesis timing misses could be very difficult to fix during implementation.

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Registered: ‎01-16-2013

Re: issues with different timing in synthesis and implementation


As Muzaffer already mentioned that the difference between post-synth timing and post-route timing. You can take the post-synth timing as reference to find out the gaps.
Gaps at the constraint level and the gaps which you really have to fill by changing some RTL. Post-synthesis you can extract lot of approcimated information of timing and as design can take a call, whether this sort of violations need to be handle using some extra constraints for ex. exception/clock_groups etc. or have to go through normal worst case single cycle calculations.

So overall, if you are getting timing fixed at post-synthesis is good if not go and check the final result at post-route. If post-route timing is not met then you really need to worry and start working to close timing for your design.

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