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Participant
Participant
883 Views
Registered: ‎08-29-2017

maximum frequency for a code in ise and vivado

hi

which section of summery report is for maximum frequency in a vhdl code?

is that  the posrt_par static timing for this frequency in ise?

witch section is the maximum frequncy in vivadio ?

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Teacher
Teacher
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Registered: ‎07-09-2009

maximum frequency does not exist in FPGA's ,,,

 

there are many many variables the placer tools optimises to meet timing and IO constraints.

 

The old CPLD days, there was max toggle frequency of a register, sort of useful,

 

   but that is all but irrelevant to big FPGA's

 

where the chip routing delay is much larger than the gate delay.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Advisor
Advisor
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Registered: ‎04-26-2015

Vivado uses quite a different timing system to ISE, and one of the results of that is that it doesn't output a maximum frequency.

 

In ISE, the tools would essentially set up everything as well as they could, and then give you a timing report. Sometimes that was much better than needed, sometimes it was worse than needed. The maximum frequency is reported, as you've found.

 

In Vivado, the tools try one approach, then they tear up the sections that didn't work so well and re-plan those, and repeat either until they decide it's impossible or they pass timing. What this tends to mean is that the design will  only barely pass timing - as soon as it passes (even if only by 1ps) the tools stop. The good news is that Vivado can now achieve a timing pass more often than ISE could (because it's a much more intelligent tool). The bad news is that you never get much in the way of headroom.

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