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Participant
Participant
2,989 Views
Registered: ‎08-15-2016

mmcm CLOCKOUT1 high fanout

In the timing summary report I can see that I have timing issues (high fanout = 15136) from the  CLOCKOUT1  of the mmcm.

 

Relevant schematic is attached, and the timing report.

 

How can I fix the timing issue from the CLOCKOUT1  of the mmcm (e.g   Source:                 clk_rst_ctrl_i/clk_wiz_0_i/inst/mmcm_adv_inst/CLKOUT1,   Destination:            rx_top_i/demoder_i/corr_res_i/rd_ptr_reg[1]/CE)

 

p.s

I use phys_opt_design command.

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clk_wiz.PNG
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Xilinx Employee
Xilinx Employee
2,984 Views
Registered: ‎08-01-2008

refer this ARs
https://www.xilinx.com/support/answers/9410.html
Thanks and Regards
Balkrishan
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Guide
Guide
2,970 Views
Registered: ‎01-23-2009

This is the same thing as your other post.

 

A high fanout of a clock is expected - this is why the clock buffers exist. But they are only used to drive clock pins of clocked cells.

 

Here again, you have the clock signal driving the CE of a cell - this is not a clock pin, and hence should never be directly reached by a clock signal - either directly from the MMCM or through a clock buffer.

 

Avrum

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Moderator
Moderator
2,801 Views
Registered: ‎11-09-2015

Hi @sarit8,

 

If everything is clear for you on this subject, please mark the thread as solved.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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