09-06-2019 01:16 PM
I am trying to learn the essentials of System Design Timing rules.
So , I made a simple design consisted of Clocking Wizard IP and DDS IP, as shown below :
I increased clk_out1 to 400 MHz frequncy, then I ran the Implementation process , but the design failed to meet the timing requirments. As shown below:
There is only one Failing End Point caused by Path 1 .
What I can do in order to fix Path1, in order to meet the Timing? (Without decreasing clk_out1 frequency)
09-06-2019 01:22 PM
Have you already applied path constraints? (One trick I have found, is that when you apply the path constraint, don't be greedy. e.g. ask for just something better (e.g. 1 ns) rather than the full amount needed. Sometimes that is enough to allow a timing closure and sometimes get 'more' than what you need.)
If your design uses LUTs, you 'may' get some benefit of setting the -no_lc flag in the synthesis section. (This may use a few more LUTs, but may improve the routing)
Hope that helps
09-06-2019 01:29 PM
Hi @xilinxacct ,
(One trick I have found, is that when you apply the path constraint, don't be greedy. e.g. ask for just something better (e.g. 1 ns) rather than the full amount needed. Sometimes that is enough to allow a timing closure and sometimes get 'more' than what you need.)
Could you please elaborate more on this .
09-06-2019 01:39 PM - edited 09-06-2019 01:45 PM
When you specify the the path constraint, I have found that it is often better to not ask for the full amount of time to but just asking for something better. That can sometime encourage the router to improve the situation, however, when asking for 'all' of the improvement still says it can't resolve it. So, if the current problem path is X ns too much, apply a constaint that is 1ns better than what it currently is, rather than making the constraint X ns less. It tends to nudge the router in the right direction.
Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)
09-09-2019 12:26 PM
09-09-2019 03:53 PM
09-09-2019 04:22 PM
Several docs and videos cover it, which can be found via search on xilinx.com or on a web search engine (just make sure to indicate your Vivado release when searching Google, etc...).
Here are 2 links you should take a look at:
09-09-2019 04:25 PM
True, although you can hit 700MHz+ on US+ medium speedgrade. Small designs can run faster and take less effort to tune.
In the case of this thread, the violation is 22ps, which should be addressed when increase the tool effort.
There is a pulse-width violation, which could be either min_period, max_period or max_skew. Except for max_skew violations, they usually point to HW running faster than what the datasheet indicates.
09-10-2019 11:35 AM
I set Performance_Explore as the implemetation strategy. However, TNS timing is met but the pulse-width still voilated.
How to indicate the reason behind the pulse-width voilation? According to your post it could min_period, max_period or max_skew.
What I can do for min_period or max period?
09-10-2019 11:41 AM
09-10-2019 11:44 AM
400MHz will be tough on a -1 Artix. He might be able to eke out 22pS, but this will be really hard to add to.
09-10-2019 02:03 PM - edited 09-10-2019 02:04 PM
It seems "min_period" the reason for the voilation. What I can do to fix it?
Take a look at the datasheet for the Artix-7 (DS181).
Specifically look at table 30, under the fMAX_* parameters. These are showing you the maximum operating frequency for the BRAM cells in various operating modes. In the Artix-7 in the -1L speed grade, these are all less than 400MHz - between 300MHz and 388MHz.
This is telling you that the BRAMs will simply not operate (reliably) at 400MHz in this device/speed grade. This can't be "fixed" - if you use BRAMs they need to operate below the fMAX rating for the mode/device/speedgrade you are using.
09-10-2019 02:52 PM
09-10-2019 02:53 PM
09-11-2019 11:00 AM
09-11-2019 11:07 AM
Also a lot of your placement is going to be on trying to get the signals to the output, Put some more output registers on the outputs is always a good idea if you trying to get a performance test.
Could you please instruct me about how to "put some more output registers on the outputs" ?
09-11-2019 11:58 AM
09-11-2019 12:01 PM