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Anonymous
Not applicable
10,723 Views

no clocks in design

Hai,

 

      I am using Vivado, kintex-7. After synthesis, i am doing timing analysis. but report_clocks showing no clock found in the design. But i defined the clock as fallows

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6 Replies
balkris
Xilinx Employee
Xilinx Employee
10,717 Views
Registered: ‎08-01-2008

http://www.xilinx.com/support/answers/55248.html
Thanks and Regards
Balkrishan
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graces
Moderator
Moderator
10,713 Views
Registered: ‎07-16-2008

Did you receive any critical warning with regards to the create_clock command?

What's the clocking topology like?

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Anonymous
Not applicable
10,706 Views

hai,

 

   no critical warning. I am using board clock coming from oscillator

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balkris
Xilinx Employee
Xilinx Employee
10,704 Views
Registered: ‎08-01-2008

can you please send your code. I would like to reproduce at my end
Thanks and Regards
Balkrishan
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Anonymous
Not applicable
10,702 Views

hai,

 

    i can't send design.. when i give command report_clocks, showing

 

WARNING: [Vivado 12-3502] Design has no clocks defined.

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viviany
Xilinx Employee
Xilinx Employee
10,700 Views
Registered: ‎05-14-2008

What do you get if you run the following constraint in Tcl console in the Synthesized design?

 

create_clock -name CLK_108MHz -period 9.26 -waveform {0 4.63} [get_ports CLK_108MHz]

 

And what do you get if you then run report_clocks after running the above constraint?

 

-Vivian

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