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Visitor
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Registered: ‎02-07-2012

no_output_delay warning for generated clock

I have two output pins in my design, which produce warnings:

 

one output signal AD5686_SCLK is used as a clock on an external device. In the Vivdo 2017.4 design, I have constraints:

 

# AD5686 DAC @12.8 MHz
create_generated_clock -name ad5686_sclk -source [get_pins ad5686_i/sclk_reg/C] -edges {1 3 5} [get_ports AD5686_SCLK]

 

the "Report Timing Summary" reports this pin as "Ports with no output delay but with a timing clock defined on it or propagating through it"

 

Is there any additional constraint that I could add to make this warning go away? Does the warning have any negative side effects?

 

The other problem is an output pin called "AD5686_SDIN" which is constraint like this:

 

# setup time relative to falling edge of sclk (5ns for AD5686)
set_output_delay -clock [get_clocks ad5686_sclk] -clock_fall -max 5.000 [get_ports AD5686_SDIN]
set_multicycle_path -setup -start -from [get_pins ad5686_i/sdin_reg/C] -to [get_ports AD5686_SDIN] 1


# hold time relative to rising edge of sclk (5ns for AD5686)
set_output_delay -clock [get_clocks ad5686_sclk] -clock_fall -min -5.000 [get_ports AD5686_SDIN]
set_multicycle_path -hold -start -from [get_pins ad5686_i/sdin_reg/C] -to [get_ports AD5686_SDIN] 1

 

here is have a warning "An output delay is missing on AD5686_SDIN relative to clock(s) HS_CLKon the "Report Methodology" output.

 

Indeed, there is no output delay relative to the internal "HS_CLK", which is the main clock for all registers, but there is an output delay defined relative to the generated clock "AD5686_SCLK", which is defined as a generated clock relative to "HS_CLK" as shown above. (ad5686_i/sclk_reg has HS_CLK (named clk25_6_BUFG in the schematic) as its clock)

 

I have attached the schematics for the clocking of the registers for AD5686_SCLK and AD5686_SDIN.

 

How do I fix my constraints to make the warnings go away?


Thanks for any help,

 

Peter

 

 

 

 

 

AD5686_SCLK.png
AD5686_SDIN.png
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5 Replies
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Guide
Guide
2,621 Views
Registered: ‎01-23-2009

Re: no_output_delay warning for generated clock

Is there any additional constraint that I could add to make this warning go away? Does the warning have any negative side effects?

 

These two questions are related. As constrained you have defined a relationship between the output clock and the output data - assuming this is correct, this assures that the interface works correctly.

 

But you haven't specified any timing relationship between the input clock and the output (forwarded) clock. Specified like this, you are leaving the phase relationship between these unconstrained and hence undefined. For most applications, this is fine - as long as the relative relationship between the forwarded clock and data is met, we are happy.

 

But, there are conditions where you care not only about the relative timing between forwarded clock and forwarded data, but also about relationship between this interface and "the rest of the system" - you care when this forwarded clock occurs. If this is the case, then you can, in addition to the create_generated_clock on the forwarded clock port, also put a set_output_delay on this port with respect to the input clock.

 

Avrum

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Visitor
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Registered: ‎02-07-2012

Re: no_output_delay warning for generated clock

Hi avrumw

 

thanks for your answer!

 

Indeed only the relationship of the forwarded clock and data matters in this application.

 

The relationship between between internal clock and forwarded signals is not important.

 

How can I constrain the relationship between the internal clock and the forwarded signals so that

 

- Warnings go away

 

and

 

- The constraints regarding the relative relationship of the forwarded signals are still correct and valid

 

Again, thanks for you help,

 

Peter

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Guide
Guide
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Registered: ‎01-23-2009

Re: no_output_delay warning for generated clock

How can I constrain the relationship between the internal clock and the forwarded signals so that

 

As I said - in addition to the create_generated clock on the forwarded clock on this port, you can also specify a set_output_delay with respect to the input clock. If you don't care about the timing, then just make up the values for the set_output_delay - make the max big and the min 0 - and it will pass. This constraint will not interfere with the constraints you already have on the other ports that use the generated clock as the reference.

 

Avrum

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Visitor
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Registered: ‎02-07-2012

Re: no_output_delay warning for generated clock

Hi Avrum,

 

thanks again for your reply.

 

you said for a dummy output delay "make the max bug and the min 0", I tried that, result am getting timing violations.

 

The opposite works, a big (postiive) min, and zero for max?

 

I am now using:

 

for a source synchronous clock output

 

create_generated_clock -name ad5686_sclk -source [get_pins ad5686_i/sclk_reg/C] -edges {1 3 5} [get_ports AD5686_SCLK]

 

set_output_delay -clock [get_clocks HS_CLK] -min 100.0 [get_ports AD5686_SCLK]
set_output_delay -clock [get_clocks HS_CLK] -max 0.0 [get_ports AD5686_SCLK]

 

to get rid of the "missing output_delay" warnings.

 

is this correct or did I misunderstand your answer?

 

Thanks for your help,

 

 

Peter

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Guide
Guide
2,540 Views
Registered: ‎01-23-2009

Re: no_output_delay warning for generated clock

you said for a dummy output delay "make the max bug and the min 0", I tried that, result am getting timing violations.

 

Sorry - you are right - for output delays the max represents the setup time and the min the negative hold time. You should put 0 for both...

 

Avrum

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