I am trying to specify output offset constraints on a source synchronous device.
in this i am sending out clock and data simultaneously. in this data is driven by a pad clock (pad_clk) and the ouput clock (clk_out) is the output of DCM 24Mhz.
the min delay between the clk and data should have 2.1 ns.
i specified the offset of 24ns on the data path. it is meeting the timing with a 17.26 ns.
On the clock path i saw delay from the DCM output to output clock port is 10ns. when i dump this bitcode on the virtex6 device i am not seeing any response. but if i shift the clock by 180 degrees i am able to get the response.
could you please add your valuable suggestion to my query.
Have you considered using the falling edge of the 24MHz clock to register the output data?
Are you using an ODDR block to generate the 24MHz output clock from the 24MHz DCM output? This is the customary implementation for generating output clocks from a fabric clock of the same frequency. See this thread for the simple explanation.
-- Bob Elkind
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