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Visitor gopal@123
Visitor
176 Views
Registered: ‎04-01-2019

post implementation Timing Simulation in vivado 2018.3

Hello Sir,

I am student working on 7 series FPGA. I would like to know about the difference between the "post implementation timing simulaton" ,"post synthesis timing simulation" and the timing that observe after the design implemented in the Hardware (FPGA).

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2 Replies
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎05-22-2018

Re: post implementation Timing Simulation in vivado 2018.3

Hi gopal@123 ,

Post-Synthesis timing simulation uses the estimated timing delay from the device models and does not include interconnect delay.

Post-Implementation timing simulation uses actual timing delays.

Please check page no. 68 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug900-vivado-logic-simulation.pdf

Also check this AR# link:

https://www.xilinx.com/support/answers/63988.html

Thanks,

raj

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Visitor gopal@123
Visitor
130 Views
Registered: ‎04-01-2019

Re: post implementation Timing Simulation in vivado 2018.3

It was really helpful answer.
Thanks for quick reply.

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