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Adventurer
Adventurer
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Registered: ‎11-15-2010

propagation delay matching for DDR2 memories

Hello,

I’m simulating my pcb layout DDR2 / XC6SLX150T. I simulated BA0 and RAS_N paths, which are exactly matched in propagation delay, but the simulation shows an important delay (more than 50 ps) between the 2 paths due to the RAS_N/BA0 Ibis INPUT and Output Models. What’s the difference between BA0 and RAS_N inputs / outputs? Should I trust the simulation for matching delays? It would lead to a significant length difference…

 

It seems that Control signals do not have any internal termination (set by ODT). But I did not see anywhere that I should terminate them by an off-ship resistor. Why? Should I terminate those signals by resistors?

 

Thanks.

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Instructor
Instructor
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Registered: ‎07-21-2009

I simulated BA0 and RAS_N paths, which are exactly matched in propagation delay, but the simulation shows an important delay (more than 50 ps) between the 2 paths due to the RAS_N/BA0 Ibis INPUT and Output Models.

 

I don't know the source of the 50pS timing difference between the two paths, but 50pS is inconsequential.  I wouldn't worry about it.  Here are the useful considerations for the circuit board routing of the address/control group signals:

 

  • Address/Control group signals are registered at the DRAM by the memory CLOCK (diff pair) rising edge.
  • Minimum setup and hold times for Address/Control signals with respect to CLOCK are 250-500pS (based on Micron 1Gbit DDR2 datasheet)
  • There is likely to be ample setup timing margin for the Address/Control signals, as these signals are unidirectional and single-data-rate.
  • Hold timing margin is provided (primarily) by the clock-output delay of the FPGA output registers, and is likely to be considerably smaller than setup timing margin.
  • It would be prudent to conserve the smaller hold timing margin.  By keeping Address/Control routing delays no less than CLOCK (pair) routing delays, hold timing margin is preserved (with small, inconsequential setup timing margin reduction).

It seems that Control signals do not have any internal termination (set by ODT). But I did not see anywhere that I should terminate them by an off-ship resistor. Why? Should I terminate those signals by resistors?

 

In DDR2 systems, termination for DQ and DM signals are provided by the DRAMs (ODT, or On-Die Termination) for WRITE operations and provided by the memory controller for READ operations.  The Address/Control group signals, however, must have termination supplied.  In the case of Spartan-6 memory systems, which are limited to single-DRAM, there are two options for termination of Address/Control group signals:  parallel termination and series termination.

 

1.  Parallel termination to 0.9V, with termination resistors placed at the end of the circuit board traces.  Usually a special-purpose DDR termination supply regulator is used to generate the 0.9V termination supply, because the regulator must be able to both source and sink current from the 0.9V supply.  Typical parallel termination resistor value is 49.9 ohms.  Parallel termination is an effective design approach for both single device (single load) memory systems and multi-device memory systems.

 

2.  For single-device (single load on each signal) memory systems, the unidirectional DDR2 Address/Control group signals can be terminated with series termination, and no termination supply (or regulator) is needed.

  • The aggregate series termination resistance includes the intrinsic Spartan-6 output driver resistance.
  • The aggregate series termination resistance should approximate the circuit board trace impedance.

For Spartan-6 designs, you have the option of

  • providing an external series resistor (should be located near the FPGA output -- driver -- pin)
  • using one of the output termination options available with Spartan-6 output cells (e.g. OUT_TERM=UNTUNED_25)
  • using only the intrinsic output driver impedance, and nothing more (e.g. SSTL18_I IBIS model indicates typical output impedance of 50 ohms)

I hope this helps explain DDR2 system termination practices and options.

 

-- Bob Elkind

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Instructor
Instructor
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Registered: ‎07-21-2009

This is the simple version of the answer to your original post.

 

I simulated BA0 and RAS_N paths, which are exactly matched in propagation delay, but the simulation shows an important delay (more than 50 ps) between the 2 paths due to the RAS_N/BA0 Ibis INPUT and Output Models.

 

The 50pS difference in delay is too small to be important.  Just make sure that both signals (and the rest of the Address/Control group signals) have roughly the same circuit board routing delay between the FPGA and the DRAM as the memory CLOCK diff pair signal.

 

It is better to have the Address/Control signals a little bit longer (rather than shorter) than the CLOCK pair signals.

 

It seems that Control signals do not have any internal termination (set by ODT). But I did not see anywhere that I should terminate them by an off-ship resistor. Why? Should I terminate those signals by resistors?

 

The two conventional termination methods for the Address/Control group signals are:  parallel and series.  You can use either method.  In the case of a single-DRAM Spartan-6 DDR2 design, the simplest method is series termination.

 

Series termination means: insert a resistor between the signal driver (the FPGA) and the signal receiver (the DRAM).  The value of this resistor should roughly match the transmission line impedance of the circuit board signal trace (usually 50 ohms).

 

In the case of Spartan-6 designs, the impedance of the Spartan-6 signal driver (SSTL18-I IOSTANDARD) closely matches the desired series resistor value.  This means you can skip the external series resistors on the board, and the intrinsic Spartan-6 output buffer characteristics should work well without any additional components.

 

-- Bob Elkind

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Adventurer
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Registered: ‎11-15-2010

I saw today that for 2 identical lines (receiver and transmission line exactly the same), two output buffers have an important difference of behaviour . (XC6SLX150T)

I measured by simulation that my DQS0 driver is around 40ps faster than my DQS7 driver. This means I should simulate every net because propagation delay matching is not sufficient.

 

I'm really wondering how can the pins have such an influence! Is there any other parameter I forgot to consider that can make a difference in driver response?

 

I attached the simulation of two DQ driver response for two identical loads (lines).

Driver mismatch.jpg
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Instructor
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I'm really wondering how can the pins have such an influence!

 

I would assume that not all package pins have identical connections to the die.  They vary in length and impedance.  The Spartan-6 family typically uses wire-bonding from package to die.  You can draw your own conclusions.

 

This means I should simulate every net because propagation delay matching is not sufficient.

 

You must have a very special application, if 40pS skew is noteworthy.  What would constitute sufficient propagation delay matching, for your purposes?

 

A minor nit:  I think you intended DQ0 and DQ7, rather than DQS0 and DQS7.  Spartan-6 MCB and MIG do not support more than two DQS (strobe) pairs, I believe.

 

-- Bob Elkind

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Xilinx Employee
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Registered: ‎11-28-2007

IBIS models include inductance (L) and capacitance (C) of each pin. L/C contribute to the flight time from the die to the package, so different pins with different L/C will have different flight times. See the AR below for additional information:

 

http://www.xilinx.com/support/answers/34174.htm

 

FWIW, ADEPT extracts LC values from IBIS models and calculates the flight time using formula in AR34174.

 

http://myadeptblog.blogspot.com/2010/11/calculate-io-flight-time-using-ibis.html

 

 


@eteam00 wrote:

I'm really wondering how can the pins have such an influence!

 

I would assume that not all package pins have identical connections to the die.  They vary in length and impedance.  The Spartan-6 family typically uses wire-bonding from package to die.  You can draw your own conclusions.

 

This means I should simulate every net because propagation delay matching is not sufficient.

 

You must have a very special application, if 40pS skew is noteworthy.  What would constitute sufficient propagation delay matching, for your purposes?

 

A minor nit:  I think you intended DQ0 and DQ7, rather than DQS0 and DQS7.  Spartan-6 MCB and MIG do not support more than two DQS (strobe) pairs, I believe.

 

-- Bob Elkind




Cheers,
Jim
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Adventurer
Adventurer
9,791 Views
Registered: ‎11-15-2010

Hello Bob, and thanks for your help.

 

UG388 page 42 gives guidelines for DDR memory interface routing.

 

Regarding DQx signals, It's said:

"There should be a maximum of +/- 25ps electrical delay (+/- 150mil) between any DQ/DM and its associated DQS strobe."

 

The skew caused by the package seems to be in this case really significant. But perhaps those guidelines are too restrictives...?

 

I will run the memory at 667Mbps.

 

 

 

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Instructor
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Registered: ‎07-21-2009

But perhaps those guidelines are too restrictive...?

 

Yes, I think they are.  What do you think?

 

I guarantee that I cannot *prove* that the guidelines are too restrictive -- I do not know enough about the silicon characterisation or the Spartan-6 MCB design to make an airtight proposition.  But I can surely come up with context information which 'shoots holes' in the guidelines.

 

The safe and bulletproof conservative approach would be to follow the very letter of the guidelines, without question.  Actually, there is one question you might wish to ask (this may require a webcase):

 

Do the circuit board layout delay-match guidelines include only the circuit board traces, or do they also include the package pin-to-pin skews?

 

  • On the other hand, if you have reliability problems with the memory sysytem, how do you explain to your project manager that you decided to exceed the published Xilinx layout guidelines (especially if your project manager isn't an engineer) ?

Tough choices to make.  That's why we design engineers are so highly paid and well-respected!

 

-- Bob Elkind

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Instructor
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I can recall, in particular, only two Xilinx recommendations which I've challenged in these forums -- both of which are mostly inconsequential (for the curious, see here and here).  This post describes a third challenge.

 

The subject is the layout guidelines for Spartan-6 memory interface, as described in UG388 version 2.3.  More specifically, the signal delay matching guidelines.

 

WARNING: It's not much trouble to challenge the certainty of the UG388 board layout guidelines, but I cannot offer a set of guidelines to take its place -- which can withstand a similar challenge.

 

Here are the points of challenge, in no particular order:

 

1.  The layout guidelines are not accompanied by assumptions, and these assumptions bear directly on the guidelines.  Specifically:

 

  • Which DRAM (and AC characteristics set) is used as a reference.  If the reference DRAM is slower (greater skew) than the actual DRAM in use, then guidelines can be relaxed to the extent of the additional timing margin.
  • Memory clock frequency baseline reference is unspecified.  If the DRAM is being clocked at a lower frequency than the timing reference design, then certain guidelines are unnecessarily tight.  This applies specifically to unidirectional single-data-rate signals (e.g. address/control group).
  • Which device package is used for timing reference.  There are additional propagation delay skews in the FPGA package, and a conservative set of guidelines would account for the very worst package and pinout combinations.  The actual design may well use a package with better-than-worst-case pin skew characteristics, which would directly add to timing margins (and allowable layout mis-match tolerances).

 

2.  Likely design opportunities for improving timing margins.  These are a few realistic and useful design considerations which should have a direct influence on layout guidelines.  Specifically:

 

  • Layout guidelines call for DQ - DQS delay matching to within 25pS (150 mils).  These guidelines specifically account for DRAM DQ setup and hold time specification with respect to DQS strobe (for write transactions) and DQS to DQ min/max output delay specification (for read transactions).  Examining a current Micron DDR2 datasheet, these byte lane timing margins for DDR2-800 devices are at least 80pS greater than for DDR2-667 devices.  DDR2-800 devices are also less expensive and more readily available than DDR2-667 devices, based on current market pricing conditions.  Using the DDR2-800 devices increase timing margins (better than reference design used to derive layout guidelines) and reduce product cost!
  • Layout guidelines call for Address/Control delay matching to CK (clock) within 50pS.  The timing margin calculations must account for DRAM minimum setup and hold specifications.  As in the case for the byte lane signals, 'upgrading' from DDR2-667 devices to DDR2-800 devices directly improves both setup and hold timing margins (each) by 25pS.

3.  The special case of Address/Control group signals (long and full of minute details):

 

  • Address/Control group signals are single-data-rate, and unidirectional.  If the circuit board delays for these signals are (uniformly) increased (relative to memory CLOCK delay), setup time margin at the DRAM is reduced, and hold time margin is increased.
  • A conventional practice for calculating (deriving) timing margins is to balance percentages rather than balance magnitudes.  For example, setup and hold timing margins for address/control signals may have been formulated to provide 10% timing margin.
  • Setup time margin is based primarily on clock period, so 10% setup margin would be roughly 250pS for DDR2-800 designs (400MHz clock, 2.5nS clock period).  Hold time margin is not affected by clock frequency, but is based on DRAM hold time and FPGA minimum clock to output delay.  Because of this difference, a 10% margin in hold timing would be much much smaller in magnitude than 10% setup timing margin.
  • A DDR2-667 design, compared to a DDR2-800 design, would add another 500pS to setup timing margin, and would add nothing at all to hold time margin.  It makes sense to balance these two timing margins.  In other words, it would be prudent and reasonable to ensure that the address/control signal delays are roughly 250 pS (1.6 inches!) longer than memory CLOCK delay.

 

To repeat myself:  Because I do not have specific knowledge of the assumptions and reference baselines which were used to formulate the UG388 board layout guidelines, it is impossible to challenge the formulations with certainty.  Having said that, maybe I've helped explain some of the fundamental considerations for the FPGA (and layout) designers using the Spartan-6 memory controller, specifically, and memory systems (generally).

 

For those designers who wish to avoid this level of minutiae, the Xilinx UG388 guidelines are the safety net to be used, and provide a measure of calm and confidence when sleeping at night.  The value of this sense of assurance should not be dismissed or under-appreciated.

 

-- Bob Elkind

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Teacher
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Registered: ‎09-09-2010

"For those designers who wish to avoid this level of minutiae, the Xilinx UG388 guidelines are the safety net to be used, and provide a measure of calm and confidence when sleeping at night. The value of this sense of assurance should not be dismissed or under-appreciated."

Especially when the equipment is fitted in passenger-carrying aircraft!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Adventurer
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Registered: ‎11-15-2010

Quality summary!

I'll need some time to fully understand the 3rd point and to learn not to drown in DDR datasheets...

I posted a webcase about the skew caused by the package.

 

Thanks.

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Instructor
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Registered: ‎07-21-2009

I'll need some time to fully understand the 3rd point and to learn not to drown in DDR datasheets.

 

This is actually the simplest of the points.  It's a matter of register to register transfer, with a common clock.  In the diagram below:

 

  • Address/Control signals are registered at the FPGA output and re-registered at the DRAM input by the same memory CLOCK. (This may not be the exact implementation, but should be a reasonable approximation)
  • There are two timing specs to meet at the DRAM:  SETUP and HOLD for Address/Control signals with respect to CLOCK rising edge.
  • If the Address/Control signals prop delay from FPGA to DRAM exactly matches CLOCK delay from FPGA to DRAM, then timing margins for Address/Control (with respect to CLOCK) at the DRAM input are simple to calculate.
  • SETUP margin is OK as long as CLOCK >Q delay (max, FPGA) plus T-setup (DRAM) is less than CLOCK period. CLOCK period is pretty large (2.5-3 nS), so SETUP margin is pretty large.
  • HOLD margin is OK as long as CLOCK>Q delay (min, FPGA) is larger than T-hold (DRAM).  But HOLD margin is probably quite small (maybe 10s of picoseconds) compared to SETUP margin.
  • If the Address/Control path is shortened a bit, advancing the signal timing at the DRAM, then T-hold (DRAM) is violated.  HOLD margin goes negative.
  • If Address/Control path is lengthened, delaying the signals at the DRAM, then the slender HOLD timing margin is increased.  This reduces SETUP margin a bit, but SETUP margin is much larger than HOLD margin to begin with.
  • Conclusion:  Best balance of SETUP and HOLD margins (for Address/Control group) is to make Address/Control board delay longer than CLOCK board delay.  (Guidelines say make the two delays equal)

 

       FPGA                                              DRAM

     +-------+                                         +---------+

     |       |A      Address/Control group            B|         |

  ==>| D   Q |========================================>| D     Q |====>

     |       |                                         |         |

     |       |                                         |         |

     |  CLK <|<-----+--------------------------------->|> CLK    |

     |       |X     |       1x Memory Clock           Y|         |

     +-------+      |                                  +---------+

     +-------+      |

     |       |      |

     |  CLK  |------+

     |   ^   |

     +--/-\--+

         |

         |

   2x Memory Clock

 

                 ___________________                     ___________________         

CLOCK(X)  ______/                   \___________________/                   \____________

            _______________ _______________________________________ _____________________

ADR/CTRL(A) _______________X_______________________________________X_____________________

                         ___________________                     ___________________

CLOCK(Y) (at DRAM) _____/                   \___________________/                   \____

                  ______ _______________________________________ ________________________

ADR/CTRL(B) short ______X_______________________________________X________________________

                    _____________ _____________________________________ _________________

ADR/CTRL(B) nominal     |<-hold->X <--------setup-------------> |      X                 

                 _____________________ _______________________________________ __________

ADR/CTRL(B) long _____________________X_______________________________________X__________

Does it make sense now?

 

  -- Bob Elkind

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Instructor
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@rcingham wrote:
"For those designers who wish to avoid this level of minutiae, the Xilinx UG388 guidelines are the safety net to be used, and provide a measure of calm and confidence when sleeping at night. The value of this sense of assurance should not be dismissed or under-appreciated."

Especially when the equipment is fitted in passenger-carrying aircraft!

Especially when someone you know might be one of the passengers!

 

-- Bob Elkind

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Hi Bob,

 

Thanks for carefully detailling your answers.

 

I calculated flight times for a couple of pins of XC6SLX150T FG676 package.

I attached the table.

 

Time Flight is really different depending on the pin considered! I hope Xilinx verifies and tests carefully the Package Models...

 

 

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Teacher
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@eteam00 wrote:

@rcingham wrote:
"For those designers who wish to avoid this level of minutiae, the Xilinx UG388 guidelines are the safety net to be used, and provide a measure of calm and confidence when sleeping at night. The value of this sense of assurance should not be dismissed or under-appreciated."

Especially when the equipment is fitted in passenger-carrying aircraft!

Especially when someone you know might be one of the passengers!

 

-- Bob Elkind


Actually, that wasn't my concern. The aircraft carrying the equipment were twin-turboprop types much sold to American operators. When an American "commuter plane" crashed (not often, but often enough) I wanted to know the manufacturer/type/series ASAP so as to be content that it couldn't have been "my box" that might have caused the incident. Perhaps a rather selfish anxiety, but also quite a common one...

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
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Time Flight is really different depending on the pin considered!

 

Again, the 55pS range is a figure that I would not consider all that astonishing or worrisome.  And it is certainly not 'scary', as your post's subject header declares.

 

I hope Xilinx verifies and tests carefully the Package Models.

 

The IBIS models you are using are evidence that Xilinx is quite meticulous in their package characterisation.

 

If you are fascinated with the notion that there is 10s of picoSeconds of flight time difference between the various pins of a 676-pin package, then by all means carry on with your work.  If you are interested in matching interconnect delays of a DRAM controller interface to the finest possible usable degree, then you are comparing the wrong sets of pins in your spreadsheet.  Your interest should then be focused within individual and entire byte lanes.

 

It sounds like you are quite enjoying your newly found insight.  You should be more careful in your choice of words.  Tossing the word 'scary' around and about is neither helpful nor reasonable.

 

-- Bob Elkind

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Instructor
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@jimwu wrote:

IBIS models include inductance (L) and capacitance (C) of each pin. L/C contribute to the flight time from the die to the package, so different pins with different L/C will have different flight times. See the AR below for additional information:

 

http://www.xilinx.com/support/answers/34174.htm

 

FWIW, ADEPT extracts LC values from IBIS models and calculates the flight time using formula in AR34174.

 

http://myadeptblog.blogspot.com/2010/11/calculate-io-flight-time-using-ibis.html



Jim, yhubert is designing with Spartan-6, and Adept 0.44 (running with ISE 12.4 on my machine) doesn't support reading Spartan-6 IBIS models.

 

UPDATE:  Adept 0.44.2 now supports reading Spartan-6 IBIS models.  Thanks, Jim!

 

-- Bob Elkind

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1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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