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Visitor
Visitor
2,317 Views
Registered: ‎05-30-2012

puzzle about setting input delay/output delay constraints in vivado

I'm a newer of vivado.In my project,the timing will go closure if I just only set the master clock constraints in xdc.For the same project,I append the "set input delay/set output delay" constraints on the IO ports of the second time,the timing will not met. Could anyone tell me:

1,If there no "set input delay/set output delay" constraints in xdc, can I trust the bitstream generated? 

2,how  "set input delay/set output delay" influence the tool(vivado)?

 

 

thank very much!

 

 

                     strong_229

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Guide
Guide
2,287 Views
Registered: ‎01-23-2009

1,If there no "set input delay/set output delay" constraints in xdc, can I trust the bitstream generated? 

 

Generally, no. Without the set_input_delay set_output_delay there are no timing requirements on your inputs and outputs. In any system that uses synchronous communication with a device connected to it, you must ensure that the timing requirements for the interfaces are met. The verification of this comes from the input/output constraints.

 

2,how  "set input delay/set output delay" influence the tool(vivado)?

 

In some cases, the constraints on an I/O will guide the placer/router in placing the cells that receive the inputs or drive the outputs. However, in many cases, it is recommended to use the IOB flip-flops that are located in the input/output block. When this is done, the timing constraints don't actually change the behavior of the tool, but merely produce reports to indicate if the timing requirements of the interface are met.

 

Timing requirements for I/O come from the devices connected to the device - generally you use the datasheet of the device and the routing information from the board to determine the set_input_delay and set_output_delay of the I/O. If the tool then tells you that the design passes timing, you can have confidence that you are meeting the requirement of the I/O.

 

If they are not meeting timing, then you have to design the I/O of the FPGA. This generally involves choosing the "best" clocking scheme for the I/O and determining how to modify the clock/data timing relationship in order to meet the timing of the interface. This would generally involve using the phase shift of the MMCM, or an IDELAY or ODELAY... Take a look at this post on designing input interfaces...

 

Avrum

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Xilinx Employee
Xilinx Employee
2,275 Views
Registered: ‎05-14-2008

1,If there no "set input delay/set output delay" constraints in xdc, can I trust the bitstream generated? 

> Like internal paths, the input/output paths also need to meet certain requirements based on your system design. Those requirements are specified via set_input_delay/set_output_delay constraints. If you do not have those constraints, you don't know if those interfaces meet the timing.

 

2,how  "set input delay/set output delay" influence the tool(vivado)?

> In general, set_input_delay/set_output_delay constraints are more of analysis purpose, rather than guiding the tool to try to meet the requirements. Unlike the internal paths, there is not much that the tool can do to improve timing on input/output interfaces. If the timing is not met, the designer needs to analyze the timing report and change the interface structure accordingly.

 

-Vivian

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