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Observer
Observer
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Registered: ‎05-10-2018

"Register / Latch pins need pulse width check" on GTP in Vivado

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HI,

I'm beginner of Vivado. Then, I checked Vivado Timing Summary and found the message below.

I read UG906, but can't understand the impact and how to avoid this messages. Let me know the solution of it.

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pulse_width_clock*Register/Latch pins need pulse width check
・・WMSC3_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/PLL0CLK
・・WMSC3_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/SIGVALIDCLK""

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

3. checking pulse_width_clock
-----------------------------
There are 2 register/latch pins which need pulse_width check. (LOW)

 

This usually means you don't have clock constraint for those two pins so the pulse width check cannot be done.

You can check if you have clock constraint on those two pins by using get_clocks command in the implemented design.

get_clocks -of_objects [get_pins  xxxxx]

If there is not, adding "create_clock" constraint for the clock source that is driving the two pins will resolve the issue.

-vivian

 

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Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @s-kaku ,

You can try to check the result of report_pulse_width for the reported pins:

Ex: 

report_pulse_width [get_pins WMSC3_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/PLL0CLK]

report_pulse_width [get_pins WMSC3_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/SIGVALIDCLK]

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

3. checking pulse_width_clock
-----------------------------
There are 2 register/latch pins which need pulse_width check. (LOW)

 

This usually means you don't have clock constraint for those two pins so the pulse width check cannot be done.

You can check if you have clock constraint on those two pins by using get_clocks command in the implemented design.

get_clocks -of_objects [get_pins  xxxxx]

If there is not, adding "create_clock" constraint for the clock source that is driving the two pins will resolve the issue.

-vivian

 

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-------------------------------------------------------------------------------------------------
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Observer
Observer
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Registered: ‎05-10-2018

Hi, Hongh and Vivian,

Thank you so much for your reply.

As Vivian mentioned, I didn't add create_clock constaraint for these two clock signals.
Does it mean these clock pins are not worked(used) in current design?
# As a matther of fact, I do not understand AXI4 IP much where these clock exist...

If we continue not to use this clock pins, can we ignore this error as it is
or should we do other action to avoid this error?
ex) add other constaraint command or delete pin definition  etc.

# Already we apply this design data to our test board, and FPGA work properly.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Without the create_clock constraints for the two pins, you don't know if they will properly work.

The pulse width check is to examine if the clocks fed to the two pins meet the requirements on hardware.

Your design working well is probably because the clocks happen to meet the requirements.

But the safe way is to let the tool check it.

Is there any difficulty for you to create the two clock constraints?

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Observer
Observer
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Registered: ‎05-10-2018

Thank you for quick reply.
I'm sorry not to have enough knowledge.
Then I checked UG476, but now I don't understand what value I should set for frequency of these clock(for "-period" option)

Connection :
 /gtp_channel.gtpe2_channel_i/PLL0CLK =====/gtp_channel.gtpe2_common_i/PLL0OUTCLK
 /gtp_channel.gtpe2_channel_i/SIGVALIDCLK =====/pipe_lane[0].pipe_user_i/oobclk.div.oobclk_reg/Q

Should each user consider and choose proper frequency?

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Moderator
Moderator
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Registered: ‎11-04-2010

The setting of the period option of create_clock/create_generated_clock depends on the requirement of your design. 

If you have set the input clock of the PLL, the output clock of PLL will be automatically derived.

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Observer
Observer
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Registered: ‎05-10-2018

Hi,

So sorry for very late reply.

Thanks to your advice, I understand.

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