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Explorer
Explorer
9,193 Views
Registered: ‎08-23-2011

"max. freq" of a design ...

hi,

 

i implemented a design successfully in ISE 14.1 on a virtex6 FPGA. the design is running at 80M.

 

But when i look at the post PAR static report - it shows something like this - 

required period - 12.5 ns (which is the 80M req freq).

actual period - 11.0 ns 

 

i wanted to know if this "actual period" is the max. freq. the design can do while meeting all the constraints? is my understanding correct?

 

is this "actual freq" dependent on the MAP/PAR settings?

 

if the actual period stated was something like 6 ns - then does it mean that the design, for that particular clock domain, can go down to a period of 6ns (logic and rounting delays all included)?

 

how else can one find the max. freq that a design can run properly on? any other method?

 

the post PAR static timing report also mentions - Minimum period: 29.452ns{1} (Maximum frequency: 33.954MHz) in the timing summary/design statistics section. what does this indicate?

 

lastly - i see 2 sections in the actual period report - direct and derivative. what is the difference between actual period direct and actual period derivative?

 

thanks in advance for your inputs ....

 

z.

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2 Replies
Xilinx Employee
Xilinx Employee
9,173 Views
Registered: ‎04-16-2012

Re: "max. freq" of a design ...

Hello,

 

Your question was answered by this answer record: http://www.xilinx.com/support/answers/34299.htm

 

Thanks,

Vinay

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Explorer
Explorer
9,163 Views
Registered: ‎08-23-2011

Re: "max. freq" of a design ...

hi,

 

thanks for the link. this answers the 2nd part of my question - the difference between direct and derivative clock. but the speed mentioned (actual period), does it imply that's the max. freq at which the particular clock domain can work? is that the overall fmax of the design?

 

if i wanted to check the max. freq. at which my design can be implemented successfully, where can i find it? am i looking at the correct place?

 

z.

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