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Visitor petexc
Visitor
171 Views
Registered: ‎11-15-2018

"set_max_delay" for ring oscillator in RO_PUF design

Hi, I'm having problems with using timing constraints in my XDC file. I'm trying to set a maximum delay for a ring oscillator in my PUF (Physically Unclonable Function) design, this is to make sure that all the ring oscillator paths are roughly as long as each other so that it does not affect the uniqueness of the PUF (basically meaning that the ring oscillator's outputs should differ by manufacturing tolerances rather than the layout delays)

I've looked about trying to manual place and route everything, but for my design this is very unfeasible.

I'm trying to make every instantiation of my ring oscillator module have roughly the same delay through the command:

set_max_delay -datapath_only 60 -from [get_ports ro_gen[1].ro_inst/excite] -to [get_ports ro_gen[1].ro_inst/out]

"excite" is the input to the ring oscillator module, and "out" is the output.

This is the critical warning I get:

[Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_ports {ro_gen[1].ro_inst/excite}]'. ["C:/Users/Peter/Home/Projects/SV/Quartus/Xilinx_Zynq_RO_test/Xilinx_Zynq_RO_test.srcs/constrs_4/new/tem_constraint.xdc":53]

 

I've read through UG903, and from my understanding I think this error is because I can't refer ports with "get_ports" which aren't primary from the top-level module.

How can I otherwise constrain my design using XDC files? Is there another way to do this right with "set_max_delay"?

8 Replies
Explorer
Explorer
164 Views
Registered: ‎10-23-2018

Re: "set_max_delay" for ring oscillator in RO_PUF design

@petexc

Did you type in the name of the object OR did you let the system fill it in for you? If you typed it in, maybe there is a typo.

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Visitor petexc
Visitor
143 Views
Registered: ‎11-15-2018

Re: "set_max_delay" for ring oscillator in RO_PUF design

I did type it in, but I checked the port name and I think it's correct.

How do I let the system fill it in for me?

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Explorer
Explorer
140 Views
Registered: ‎10-23-2018

Re: "set_max_delay" for ring oscillator in RO_PUF design

@petexc

Optional starting point ... On the schematic... pick the initial or terminal pin (or something path) you want to constrain. Right mouse click/ timing report... then choose 'To I/o Pin' (or from, or through as applicable).

In the timing window. select the path you want to constrain... Right mouse click 'set maximum delay' ... the dialog will be filled in with the correct value... then just set the time.

Hope that helps

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Scholar jmcclusk
Scholar
119 Views
Registered: ‎02-24-2014

Re: "set_max_delay" for ring oscillator in RO_PUF design

you are using System Verilog, or Verilog, aren't you?    There's a major problem in using these languages for programmatic placement of primitive elements, because attributes are grafted in using pragmas, and aren't actually part of the language as such.

VHDL can do it, and does it very well, since LOC constraints can be calculated in the code with attributes.   Using a max delay constraint won't produce reproducible designs (in any language).    You'll get different results EVERY TIME YOU COMPILE.    If you are trying to design an actual PUF, then I suggest you write the low level ring oscillator in VHDL so you can use LOC constraints to lock down the gates to specific locations in the chip. 

Don't forget to close a thread when possible by accepting a post as a solution.
Moderator
Moderator
105 Views
Registered: ‎01-16-2013

Re: "set_max_delay" for ring oscillator in RO_PUF design

Hi,

Regarding the set_max_delay constraints the starting point should be clock pin of source element and end point should be data pin of destination element.

Also warning message clearly states that there is no port with such name. You can first check the command get_port or get_pins etc in synthesized design whether there is any valid object return then you can use it in your constraints.

Also I feel those has to be pins than ports. Ports are the only one which has IO level connection to FPGA.

Thanks,
Yash

 

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Visitor petexc
Visitor
92 Views
Registered: ‎11-15-2018

Re: "set_max_delay" for ring oscillator in RO_PUF design

Hi,

Thanks for your response. Regarding what you said about the start point for the set_max_delay constraint, what if I don't have a clock pin of a source element? Is there no way to measure the delay between the input of a chain of LUT1 primitives and the output?

Cheers,

Pete

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Moderator
Moderator
63 Views
Registered: ‎01-16-2013

Re: "set_max_delay" for ring oscillator in RO_PUF design

Hi,

set_max_delay is only for sequential elements. This is not valid for combinatoric logic.

The only way to make valid timing analysis in STA is if there is input and output ports connected with combinatoric logic using the virtual clock concept. Refer page #40  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug903-vivado-using-constraints.pdf 

I hope this will be helpful.

Thanks,
Yash

Note: You can check the set_max_delay -from and -to valid points in the same user guide.

 

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Historian
Historian
49 Views
Registered: ‎01-23-2009

Re: "set_max_delay" for ring oscillator in RO_PUF design

set_max_delay is only for sequential elements. This is not valid for combinatoric logic.

This isn't actually correct...

Before I continue, I will state that set_max_delay should be (and normally is) applied to a complete static timing path, and, as others have said, a static timing path starts at a startpoint, which is the clock pin of a clocked element or an input port, and ends at an endpoint which is the data input pin of a clocked element or an output port. When applied to a complete path, the set_max_delay overrides the requirements on that path.

However, if the -from of a set_max_delay is not a static timing path startpoint (which is specified either as a clock, a clock pin of a clocked element, the clocked element itself, or an input port), and/or if the -to of a set_max_delay is not a static timing path endpoint (which is a clock, a data pin of a clocked element, the clocked element itself or an output port) then the set_max_delay does something different. When this occurs, something called "path segmentation" occurs.

If you apply a set_max_delay -from to a non-startpoint, any static timing path that went through that point is now segmented and becomes two paths:

  • One that starts at the -from point of the set_max_delay and ends at the original paths endpoint (assuming the -to of the set_max_delay is not also a non-endpoint) - this one is constrained by the new set_max_delay
  • One that starts at the original startpoint and ends at the -from point in the set_max_delay - without any other constraints, this path is now unconstrained, even if the original path (before segmentation) was constrained

The same is true for a -to that is not an endpoint.

Path segmentation is rarely used - it is there for constraining specific kinds of designs - usually where there are combinatorial loops. This can occur in "real" designs like round robin arbiters (where the combinatorial loop is structurally present, but false), or in things like (yes, I am going to say it) ring oscillators.

More often, though, path segmentation is done in error - for example if you specify -from [get_pins my_ff/Q] instead of the correct [get_pins my_ff/C], then you will accidentally segment the path - one path from the C to the Q pin of the FF and a new path from the Q to the real endpoint of the path. This is a mistake and will result in all kinds of weird timing behaviors. As a result, the tool will warn you (I think with a Critical Warning) when you segment a path...

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