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eng_man
Explorer
Explorer
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Registered: ‎12-22-2010

rising and falling edge lfsr skew problem how to avoid

hi 

i had bulit a dual edge 4 bit LFSR random generator work on both rising and falling

some member in another group say that this desgin suffer from skew problem

i hear allot about this problem many time,i see it in user guide but i didnot understand exactlly 

so can any one give simple decribing  this problem and how to reduce it or avoided 

is thier  optimum frequency to avoid this problem!!>>>
i am really confuse. 

 lfsrworkwith rising and failling.png

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23 Replies
bassman59
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Registered: ‎02-25-2008


@eng_man wrote:

hi 

i had bulit a dual edge 4 bit LFSR random generator work on both rising and falling


Why? What problem do you think you're trying to solve by clocking something on both edges?

----------------------------Yes, I do this for a living.
eng_man
Explorer
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Registered: ‎12-22-2010

i have circuit that need 250,000 clock to get the output
so this is a huge delay
so i think to incrase freq and use dcm
or work on dual clock
so that all i need
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bassman59
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Registered: ‎02-25-2008


@eng_man wrote:
i have circuit that need 250,000 clock to get the output
so this is a huge delay
so i think to incrase freq and use dcm
or work on dual clock
so that all i need

Have you figured out whether or not the FPGA you've chosen supports flip-flops that work on both edges of the clock?

----------------------------Yes, I do this for a living.
eng_man
Explorer
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Registered: ‎12-22-2010

Have you figured out whether or not the FPGA you've chosen supports flip-flops that work on both edges of the clock?
________________
i have spartan 3e which not support dual flip-fop
i used a method to solve the problem and the result as you can see above, it work but suffer from skew as they told me.
i rad that the cpld work on dual edge
>>>>>>>>>>>>>>>>>>>>>>>>>>
also i would to tell you that my system only consist of random generator,counter ,comparator and 'and' gate
can my system avoid the problem due to this simple component?????

regards
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mcgett
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Registered: ‎01-03-2008

There will be some duty-cycle distortion on the global clock network, but if you can meet timing with both 40/60 and 60/40 duty cycles then it shouldn't be a problem.

 

I am confused as to why you are doing this.  I read that it takes 250,000 clock cycles to complete, but that the design is only comprised of a LFSR, counter, and a comparator which seems very fairly trivial.  What exactly is the design intended to do?  And why isn't running the clock at 2x speed a possible answer?

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eng_man
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Registered: ‎12-22-2010

There will be some duty-cycle distortion on the global clock network, but if you can meet timing with both 40/60 and 60/40 duty cycles then it shouldn't be a problem.

 

What the 40/60 and 60/40 mean,??

Is  clock of the Spartan 3e meat this specification??

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..

The system do a special operation that need huge clock to complete 

I think the best solution is to increase frequency by use dcm

 what is maximum can i work on spartan 3e ??

 

 

regards

 

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mcgett
Xilinx Employee
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Registered: ‎01-03-2008

40/60 and 60/40 refer to the duty cycle of the clock that you are using.  40% high/ 60% low or 60% high/ 40% low.  For a 100 MHz clock that would be 4nS/6nS and 6ns/4nS.   Since you must have data transfers in your design between the rising and falling edges you must account for the worst case timing which would be the smaller time.

 

> The system do a special operation that need huge clock to complete

I don't understand this comment.  I can understand a system needing real time delays, but it does not appear that this is true in your system.  Since you are not providing a good description of the real system problem that you are trying to solve there isn't anything more to discuss here.

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eng_man
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Registered: ‎12-22-2010

dear :mcgett
>The system do a special operation that need huge clock to complete
I don't understand this comment.
this is the system that need (2^17)-1 CLOCK TO COMPLETE

CAN I MAKE ANY CACULATION FOR THIS SYTEM AND GET WORST CAEE DELAY!!!!

 

SYSTEM.png

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hgleamon1
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Registered: ‎11-14-2011

this is the system that need (2^17)-1 CLOCK TO COMPLETE

How have you implemented your LFSRs for this MASSIVE delay to be the case?

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eng_man
Explorer
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Registered: ‎12-22-2010


How have you implemented your LFSRs for this MASSIVE delay to be the case?

this comment not clear to me??
but if you mean that is implement or not ,part of it implemeted not all

i stop because problem in the clock as i read in many post in forum 

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hgleamon1
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Registered: ‎11-14-2011

What I meant was, how have you written code for the LFSRs?

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eng_man
Explorer
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Registered: ‎12-22-2010

here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lfsr is
port ( rest,clk :in std_logic;
output :out std_logic_vector(3 downto 0) );

end lfsr;

architecture Structural of lfsr is
signal temp :std_logic_vector(3 downto 0):=(others=>'1');
signal temp2:std_logic_vector(3 downto 0):=(others=>'1');
begin
process (clk)
variable r:std_logic_vector(3 downto 0):=(others=>'1');
variable r2:std_logic_vector(3 downto 0):=(others=>'1');
variable t:std_logic:='0';
begin
if (clk'event and clk='1') then --- shift by 2
t:=r(0) xor r(1);
r(2 downto 0):=r(3 downto 1) ;
r(3):=t;
-------------------------------
t:=r(0) xor r(1);
r(2 downto 0):=r(3 downto 1) ;
r(3):=t;
--------------------------------
t:=r(0) xor r(1);
r2(2 downto 0):=r(3 downto 1) ;
r2(3):=t;

end if;
temp<=r;
temp2<=r2;
end process;

output <= temp when clk='1'
else temp2 ;

end Structural;
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hgleamon1
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Registered: ‎11-14-2011

output <= temp when clk='1' else temp2 ;

I guess you realise now that this is really bad coding practice, given the amount of discussion in this thread centred on your clock usage. To be clear, you can't use a clock signal as a selector for a mux.

 

Anyway, ignoring that, your 4 bit LFSR seems OK (quite why you repeat the assignments to t and r in the middle of your process is unknown to me), so you should get some new data out every clock cycle.

 

Assuming you do actually want new data (of this type) out every clock cycle, I fail to understand why you think that a 17 bit LFSR will have a latency of (2^17)-1 clocks, unless there is something about the data you want that you haven't told us.

 

I can look at your diagram but I still cannot tell what is you want to do .. ?

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eng_man
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Registered: ‎12-22-2010

 

 

Anyway, ignoring that, your 4 bit LFSR seems OK (quite why you repeat the assignments to t and r in the middle of your process is unknown to me), so you should get some new data out every clock cycle.

If you continue execution will find this the idea

 

if clock as selector what is the problem!!!!! 

 i happy  to know that is bad practice ?!!

double.png

 

Assuming you do actually want new data (of this type) out every clock cycle, I fail to understand why you think that a 17 bit LFSR will have a latency of (2^17)-1 clocks, unless there is something about the data you want that you haven't told us.

I can look at your diagram but I still cannot tell what is you want to do .. ?

this circuit  is an implementatiion of what is called stochastic compution

http://en.wikipedia.org/wiki/Stochastic_computing

the goal only to ecute this as fast as possible

 

 

 

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All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
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mcgett
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> this is the system that need (2^17)-1 CLOCK TO COMPLETE

 

The system does not make any sense to me.  Both of the LFSRs will run through a fixed pattern cycle taking 2^17-1 cycles to complete and assuming that both LFSR are reset to the same value at the same time unless both CONSTANT 1 & 2 are idententical the result of the comparison will never be the same, the AND gate will never be active and the COUNTER will never increment.

 

If both LFSRs are reset to the same value and at the same time and If both CONSTANT1 & 2 are identical then the COUNTER will incremement once every 2^17-1 cycles.

 

If both LFSRs are not reset to the same value or at the same time then the likelihood of having LFSR1 equal to CONSTANT1 and LFSR2 equal to CONSTANT2 at the same time has a very small probablility, but one that is determinable without going through all of the cycles.

 

There must be something else to this design, because if this is the entirety of the design then it doesn't serve any useful purpose.

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hgleamon1
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This thread has already discussed the dubious behaviours of circuits ill-designed to operate on both rising and falling edges of a clock.

 

Secondly, a multiplexer exists in fabric logic. The clock exists on the global routing. If you use the clock as a selector, you must force it off the global routing. This causes a bit of a technical headache for the tools, unnecessarily loads the clock and can be the cause of skew and delay problems for the clock tree.

 

Do you need to run the process for (2^17)-1 clocks to produce a result? If you do, you will have no option but to run it at the fastest frequency the design can handle (single edge clock, of course). For something this simple, I would have thought that 100's of MHz would be easily achievable.

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eng_man
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Registered: ‎12-22-2010

Dear mcgett:
There must be something else to this design, because if this is the entirety of the design then it doesn't serve any useful purpose.

i forget something to say about this circuit which the seed of each LFSR must be different at starting

And the constant may be equal or may be not equal depend on input

this is implementation of stochastic logic, 

it purpose will make a multiplication of two number 

so just need a large number of  clock

any suggestion related to raising and falling edge,skew??? 

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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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hgleamon1
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Registered: ‎11-14-2011

any suggestion related to raising and falling edge,skew??? 

My suggestion is: don't use both edges, just use the rising edge of a high frequency clock.

 

If it is just for multiplying numbers, I assume this is some academic project because, surely, a multiplier would be far easier (and probably return a result a lot faster, too).

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eng_man
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Registered: ‎12-22-2010

Do you need to run the process for (2^17)-1 clocks to produce a result? If you do, you will have no option but to run it at the fastest frequency the design can handle (single edge clock, of course). For something this simple, I would have thought that 100's of MHz would be easily achievable.

 

 I think I will do this and forget the dual edge

I wish if their describe to these  delay problem in fpga 

If I not post this thread I will never no know that will be a problem

So I frustrated now.

thank you

 
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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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eng_man
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Registered: ‎12-22-2010

any suggestion related to raising and falling edge,skew??? 

My suggestion is: don't use both edges, just use the rising edge of a high frequency clock.

If it is just for multiplying numbers, I assume this is some academic project because, surely, a multiplier would be far easier (and probably return a result a lot faster, too).

____________________________________________________________________

I am now convinced that the dual edge idea is not workable

and i will use higher frequency,

as you  an expert can i execute this circuit above 100MHZ on spartan 3e like 200 or more with out any clocking problem. 

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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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hgleamon1
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Registered: ‎11-14-2011

can i execute this circuit above 100MHZ on spartan 3e like 200 or more with out any clocking problem.

Well, this the engineering side of the task, isn't it?

 

There are several questions that need to be addressed before you can simply state what the likely maximum frequency of the design can be.

 

Firstly, and foremost in my opinion, is: what are your requirements? What frequency are you REQUIRED to meet? "As fast as possible" is not a requirement.

 

Then you have other considerations, like:

 

1. What is the maximum clock frequency of the device? Check the datasheet.

2. Will you have other logic blocks in the device that may affect the performance of this block? (think placement and routing)

3. What does your pinout look like? Having widespread input and outputs can affect placement and routing, thereby affecting the frequency.

4. What is your device input frequency and will you need some clock management (e.g. PLL)?

 

After these things have been considered and you have simulated your design to your satisfaction, then you can synthesise (and get a general idea of design size and performance), then you can implement the design and get real results from the PAR tools.

 

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eng_man
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Registered: ‎12-22-2010

thank you hgleamon1
i really appreciate that
just last thing what is PAR tools. i never hear about it
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I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
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hgleamon1
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Registered: ‎11-14-2011

what is PAR tools

Place And Route. Quite an important part of the implementation process.

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"That which we must learn to do, we learn by doing." - Aristotle