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Contributor
Contributor
744 Views
Registered: ‎09-07-2014

set_bus_skew timing violation


Dear Forum Members,


I use MMCM (IP-catalog generated) driven by two unrelated clocks PRI_CLK and SEC_CLK, as the primary and secondary MMCM inputs, respectively.

PRI_CLK is driven by JESD core, which its refCLK port is fed by 204.8MHz REF_CLK ; The REF_CLK is constrained with create_clock command.

SEC_CLK is driven by different MMCM, which its input is fed by 200MHz FPGA_SYS_CLK ; The FPGA_SYS_CLK is constrained with create_clock command, too.


The MMCM configured to have two outputs clocks - let's says, CLK_X2 and CLK_X1, with period determined by the selected input clock.

The output clocks are used for some asynchronoud FIFO write and read clocks (either Distributed or Block RAM-based).

After implementation completed, I got message that set_bus_skew constraint has failed.


Looking at "Path properties" tab I see that Vivado STA use SEC_CLK for sourceClockPathAnalysis and PRI_CLK for destinationClockPathAnalysis.

This, of course, not the situation I meant - only one of the clocks should be treated as the source for the MMCM outputs.

How should I direct the tool to analyze it propely (I use Vivado 2018.2) ?


Thank you all,

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4 Replies
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Xilinx Employee
Xilinx Employee
671 Views
Registered: ‎03-26-2019

Hi nissan.luzon,

There is a special timing constraint for multiple clocks on the same clock tree. Please review AR#47490. Please also let me know if this works for you.

Thanks,

Ben

P.S. Don’t forget to reply, kudo, and accept as solution

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Contributor
Contributor
644 Views
Registered: ‎09-07-2014

 

Hi bfell,

 

Thank you for your reply.

AR#49470 specify the use of set_clock_groups with -physically_exclusive option for such case.

I would like to mention that our MMCM was configured using IP catalog and delivered with such constraint (this can be verified by configuring MMCM with two input clocks and review the generated *_late.xdc file). In addition, I can see this constraint active in Vivado Constraint Editor after Opening Synthesized Design.

Nevertheless, it seems the tool somehow "skipped" this constraint when it comes to set_bus_skew checks.

So, my question was, and yet, why the tool report this? Although I can ignore this Critical Warning message (the clocks are exclusive), I don't think it's a good idea because this might have other P&R ramifications which evantually have total side-effect in our design implementation.

Appreciate your reply!

 

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Xilinx Employee
Xilinx Employee
622 Views
Registered: ‎05-11-2012

Hello,

P140 of UG903 shows the reason that the set_clock_groups exception does not affect set_bus_skew constraints:

"The bus skew constraint is not a timing exception; rather, it is a timing assertion. Therefore, it does not interfere with the timing exceptions (set_clock_group, set_false_path, set_max_delay, set_max_delay -datapath_only, and set_multicycle_path) and their precedence."

Where did those set_bus_skew constraints come from in the first place? Were they automatically generated by Vivado?

Thanks,

Ryan

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Contributor
Contributor
609 Views
Registered: ‎09-07-2014

 

Hello rcollet,

 

Thank you for your reply.

 

Considering your question  -

Where did those set_bus_skew constraints come from in the first place? Were they automatically generated by Vivado?


The answer is Yes. I can see the Vivado tool automatically generates this constraint as part of the asynchronous FIFO (to be more accurate, the constraint is generated by Tcl scripts associated with the FIFO, however, it does not appear in FIFO's XDC files listed in IP Sources tab).

 

Considering the quote below -


"The bus skew constraint is not a timing exception; rather, it is a timing assertion."


OK, what should I do now? Shall I change something in my design? I still have critical warnings...

 

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