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allien
Adventurer
Adventurer
243 Views
Registered: ‎02-28-2015

set_case_analysis with flip-flop

Hi All,

As mentioned in AR# 51464: Vivado - What scenarios are covered by set_case_analysis? (xilinx.com), set_case_analysis can be used with reset pin of a FF. I tried few example but didn't get expected result. Is this still supporting ?

Thanks

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2 Replies
viviany
Xilinx Employee
Xilinx Employee
212 Views
Registered: ‎05-14-2008

Can you elaborate what you expected from using set_case_analysis with the reset pin of FF?

And how you used the set_case_analysis?

-vivian

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allien
Adventurer
Adventurer
125 Views
Registered: ‎02-28-2015

Hi Viviany,

I have a code like below

always @ (posedge clk_in or posedge reset) begin
  if (reset) begin
      state <= STATE_INIT;
  end
  else begin
    case (state)
      STATE_INIT : begin
          clk_gen <= 1'b0;
          state <= STATE_NEXT;
      end
      STATE_NEXT : begin
          clk_gen <= ~clk_gen;
      end
      default : begin
         clk_gen <= 1'b0;
         state <= STATE_INIT;
      end
   endcase
  end
end

I have set reset as set_case_analysis 1. So I expect no timing analysis for the logic driven by clk_gen in timing summary report.

Thanks

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