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Explorer
Explorer
250 Views
Registered: ‎04-01-2016

set_false_path doesn't work

Hi all,

currently I'm doing timing closure on a prototype. Here I do have a signal called scan_mode. This signal is set once at the startup and then will not be changed any more, it is a test signal. This specific signal is used on all clock domains. A look in UG903 says what I already knew:

2018-12-22_11h51_56_ug903.png

 

I had a look in the unconstrained paths and there I saw the signal:

2018-12-22_11h55_20_scanmode.png

The schematic is the following:

2018-12-22_12h02_10_schematic.png

 

I tried to apply timing constraints, but none of the both worked, neither the "-from xxx to xxx" nor the "-through scan_mode" worked, the signal still appear in the unconstrained list:

 

# ----------------------------------------------------------------------------------------------------------------------------
# -- ignore timing from scanmode to all registers (UG903 - page 111)                                                        --
# ----------------------------------------------------------------------------------------------------------------------------

set_false_path -from [get_cells fpga_asic_dummy_inst?/scan_mode_ff_i/s_q_reg] -to [all_registers]
set_false_path -through [get_nets fpga_asic_dummy_inst1/scan_mode_zz]

When I call the get_cells and get_nets command with the shown signal and FF instance in the schematic I see that they are really available, so there is no typo inside them. I don't understand why the constraints (none of them) aren't applied to the signals.

Thanks for helping!

Kind regards

Sebastian

 

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4 Replies
Moderator
Moderator
128 Views
Registered: ‎01-16-2013

Re: set_false_path doesn't work

Hi Sebastian,

As this is old post I wanted to confirm that are you still facing this issue? If yes, let me try to help you.

Is the clock constraints provided for the registers under concern?

If you generate timing report from XXX to XXX are you able to get any reporting values?

Also when you validated the registers are present is at post-synthesis or post-implemented results?

From syntax point of view the constraints looks correct to me for false path.

Thanks,
Yash

 

 

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Scholar watari
Scholar
122 Views
Registered: ‎06-16-2013

Re: set_false_path doesn't work

Hi @sebastian_z

 

If you implement your design as ASIC prototype in FPGA, I recommend to use the following command.

 

set_case_analysis <value> <location>

 

When you this command at correct point, you can ignore scan logic.

 

ex.

set_case_analysis 0 [get_ports SCAN_ENABLE];

 

Best regards,

 

Explorer
Explorer
109 Views
Registered: ‎04-01-2016

Re: set_false_path doesn't work

@watari @yashp

Thanks for helping. Great idea with the set_case_analysis! I will try this out as soon as possible (currently I'm facing an other problem). I will let you now!

Kind regards

Sebastian

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Participant evant_nq
Participant
10 Views
Registered: ‎07-18-2018

Re: set_false_path doesn't work

Hi sebastian_z,

When I call the get_cells and get_nets command with the shown signal and FF instance in the schematic I see that they are really available, so there is no typo inside them. I don't understand why the constraints (none of them) aren't applied to the signals.

You said you get the right primitives when you do the commands stand alone, but that only proves the elements are in the design.

Make sure you can describe the timing arc you wish to false path. The way I would check that is do to:

 

 

report_timing -from [get_cells fpga_asic_dummy_inst?/scan_mode_ff_i/s_q_reg] -to [all_registers] -delay_type min_max -nworst 10 -max_paths 10 -name result_1
report_timing -through [get_nets fpga_asic_dummy_inst1/scan_mode_zz] -delay_type min_max -nworst 10 -max_paths 10 -name result_2


This should open two reports, with the first 10 paths/endpoints.


If nothing returns, then the issue is that you are not describing a timing path. And you might need to tweak the end points to make sure it grabs what you want it to

 

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