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Visitor fpgaron
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Registered: ‎05-31-2018

set_max_delay constraints

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I am trying to constrain some input to output fully combinational paths using  set_max_delay and the VHDL input and output port names. For example:

set_max_delay -from [get_ports etx1]  -to [get_ports txd_1_pmi]  5

 

I get the following warnings:

[Vivado 12-584] No ports matched 'etx1'.

[Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_ports etx1]'.

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Highlighted
491 Views
Registered: ‎01-22-2015

Re: set_max_delay constraints

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@fpgaron 

Some things to check:

  • In VHDL, port names are not case sensitive.  However, in the Vivado .xdc file, port names are case sensitive.  Best to use  ‘etx1’ everywhere (and not ‘etx1’ in some places and ‘ETX1’ elsewhere).
  • Use set_input_delay and set_output_delay on your ports as described on pg1594 of UG835(v2019.1).  

Cheers,
Mark

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4 Replies
Highlighted
492 Views
Registered: ‎01-22-2015

Re: set_max_delay constraints

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@fpgaron 

Some things to check:

  • In VHDL, port names are not case sensitive.  However, in the Vivado .xdc file, port names are case sensitive.  Best to use  ‘etx1’ everywhere (and not ‘etx1’ in some places and ‘ETX1’ elsewhere).
  • Use set_input_delay and set_output_delay on your ports as described on pg1594 of UG835(v2019.1).  

Cheers,
Mark

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Moderator
Moderator
453 Views
Registered: ‎11-04-2010

Re: set_max_delay constraints

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Hi, @fpgaron , 

Please open the synthesized design and run the below command in TCL CONSOLE to check whether the port you refer in your constraint exists.

%join [get_ports ] \n

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416 Views
Registered: ‎01-22-2015

Re: set_max_delay constraints

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@fpgaron 

-also check:

  • 'etx1' should be a port in the top-level VHDL component of your design
  • For 'etx1', you should write 'set_property IOSTANDARD' and 'set_property PACKAGE_PIN' constraints in the Vivado .xdc file
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Visitor fpgaron
Visitor
367 Views
Registered: ‎05-31-2018

Re: set_max_delay constraints

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Thanks, Mark, for pointing that out. All of my other constraints were copied and pasted form the VHDL and therefore maintained the same case. However, these constraints had the opposite case than in the VHDL. The constraints are working now.

Thanks, I appreciate it.

Ron