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Visitor snorwood
Visitor
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Registered: ‎07-02-2018

sgmii ip does not meet timing.

The XilSGMII IP core rx elastic buffer does not meet timing.  What is the best implementation strategy to ensure this Xilinx ip will meet timing.

Thanks

 

Capture1.PNGCapture2.PNG

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3 Replies
Historian
Historian
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Registered: ‎01-23-2009

Re: sgmii ip does not meet timing.

A violation of this magnitude is not going to be fixed by a tool option. This is an architectural or (more likely) constraint issue.

Looking at the net from the distributed RAM to the flip-flop (rx_elastic_buffer/dpo) we see that the tool has added a WHOPPING 9.253ns of routing delay to the net. This is in spite of the fact that the RAM and the flip-flop are very close by (the slice location is a one CLB over and one CLB up). This is a clear indication that the tool was fixing a hold time violation. When there is a hold time violation, Vivado will add routing to attempt to fix the hold violation - even if it causes a setup violation; hold has higher priority.

In this case, we see a failing setup violation caused by this large net delay. Looking at this path, there can't be a hold violation; the source (the read address flop) and the destination (the read data capture flop) are on the same clock.

However, a RAMD64E (a dual port distributed RAM) has two arcs to the dpo port

  • The read path that we are looking at here - from the RDADR to the dpo output
  • From the write clock to the dpo output

This second path is almost certainly causing the problem.

The read of a distributed RAM is combinatorial - whenever the read address changes, the data output changes to the contents of the RAM at that address location combinatorially. This is the first path.

When a write operation occurs, though, the contents of the RAM changes. The write operation is synchronous, so the RAM contents can change at the rising edge of the write clock. If the read address is currently selecting the address of the RAM that is changing, then then the data output will change as soon as the write is complete. This creates the second arc, from the write clock to the dpo output.

Since the dpo output is going to a flop on the read clock domain, this is a clock domain crossing (CDC) path. With no exceptions, the tool will treat it as a synchronous clock crossing. If the (the write clock and the read clock) are not frequency and phase matched (i.e. they are unrelated clocks) then this will cause violations - including hold violations that the tool will try and fix. This is what is likely happening here.

Now, as to the solution - this path needs to be "dealt with". If this distributed RAM is being used as a FIFO (which is likely the case), then the empty/full logic around the FIFO ensures that the read address is never selecting the address that is being written. If that is the case (and the FIFO is properly constructed with proper clock crossing on the empty/full generation) then this second path is false; it is correct to use an exception on it (either a set_false_path or a set_max_delay -datapath_only).

The only question is "Why doesn't the IP have this exception". All Xilinx IP comes with scoped constraint files, and this timing exception should be in the scoped constraint file for the SGMII IP. I would look at your log files to see if there are any critical warnings indicating that a constraint can't be processed. Otherwise we need to dig further as to why this exception is missing.

Avrum

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Visitor snorwood
Visitor
339 Views
Registered: ‎07-02-2018

Re: sgmii ip does not meet timing.

Thank you Avrum.  I was missing timing constraints.  However I still don't meeting timing with this IP. I don't think the IP constraints cover the paths I am having trouble with.  See XilSGMII.xdc GT Initialization circuitry clock domain crossing constraints below.  Thanks.

Capture2.PNGCapture1.PNG

 

 

#-----------------------------------------------------------
# PCS/PMA Clock period Constraints: please do not relax    -
#-----------------------------------------------------------


  # Clock period for the Txout clock
  create_clock  -period 16.000 [get_pins -hier -filter {name =~  *pcs_pma_block_i/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXOUTCLK}]
 

  #-----------------------------------------------------------
  # Receive Clock period Constraint: please do not relax
  #-----------------------------------------------------------
  # Clock period for the recovered Rx clock
  create_clock  -period 16.000 [get_pins -hier -filter { name =~ *pcs_pma_block_i/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXOUTCLK}]

 

set_false_path  -to [get_pins -hier -filter {name =~  *core_resets_i/pma_reset_pipe_reg*/PRE}]
set_false_path  -to [get_pins -hier -filter {name =~  *core_resets_i/pma_reset_pipe*[0]/D}]


#***********************************************************
# The following constraints target the Transceiver Physical*
# Interface which is instantiated in the Example Design.   *
#***********************************************************


#-----------------------------------------------------------
# PCS/PMA Clock period Constraints: please do not relax    -
#-----------------------------------------------------------

 

 

# Control Gray Code delay and skew across clock boundary
set_max_delay -from [get_cells -hier -filter {name =~ *pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_*_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_wr_addrgray[*].sync_wr_addrgray/data_sync*/D}] 16 -datapath_only
set_max_delay -from [get_cells -hier -filter {name =~  *pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_*_reg[*]}] -to [get_pins -hier -filter { name =~ *reclock_rd_addrgray[*].sync_rd_addrgray/data_sync*/D}] 8 -datapath_only

# Constrain between Distributed Memory (output data) and the 1st set of flip-flops
set_false_path  -from [get_clocks -of [get_pins  -hier -filter { name =~ *pcs_pma_block_i/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gt*e2_i/RXOUTCLK}]] -to [get_pins -hierarchical -filter { name =~ *rx_elastic_buffer_inst/rd_data_reg*/D } ]
set_false_path  -from [get_pins  -hierarchical -filter { name =~  *transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C}] -to [get_pins -hierarchical -filter { name =~ *rx_elastic_buffer_inst/sync_initialize_ram_comp/data_sync_reg*/D } ]


#-----------------------------------------------------------
# GT Initialization circuitry clock domain crossing
#-----------------------------------------------------------

set_false_path -to [get_pins -hier -filter { name =~ */gtwizard_inst/*/gt0_txresetfsm_i/sync_*/*D } ]
set_false_path -to [get_pins -hier -filter { name =~ */gtwizard_inst/*/gt0_rxresetfsm_i/sync_*/*D } ]

set_false_path -to [get_pins -hier -filter { name =~ */gtwizard_inst/*/sync_*/*D } ]

 

# false path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *SYNC_*/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ *pcs_pma_block_i/transceiver_inst/sync_block_data_valid/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ *sync_block_tx_reset_done/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ *sync_block_rx_reset_done/data_sync*/D }]

set_false_path -to [get_pins -hier -filter {name =~ */*sync_speed_10*/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ */*gen_sync_reset/reset_sync*/PRE }]


set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]

 

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Visitor snorwood
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Registered: ‎07-02-2018

Re: sgmii ip does not meet timing.

another occasional problem path.  Related to the reset.

 

Capture5.PNG

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