UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor stmallios
Visitor
2,296 Views
Registered: ‎01-18-2017

synch clk domains crossing advise

Jump to solution

Dear experts,

 

I am trying to cross clock domains from a 240M clk to a 160Mhz clk. The 2 clks are synchronous. At the 240 Mhz domain I use a deserialization process where I get two 32bit word every 240M clk pulse and fill a large 384-bit vector after 6 clk cycles. Then on the 6th cycle I propagate this vector to another vector . The 2nd vector will hold this information for 6 clk cycles. I want to use this vector to cross to the 160Mhz clk domain. Do you have any suggestions on what constrains should I use?

Bellow is the deserialisation process. w_data (383 downto 0) is the 1st 384-bit vector that fills after 6 cycles and the s_data is the 2nd vector that gets ovewritten every 6th clk.

 

Thank you.

 

PROCESS (clk240)
BEGIN
IF Rising_Edge(clk240) THEN
IF valid_pulse = '1' THEN
-- d_counter <= "000";
d_counter <= UNSIGNED (cntr_start);
ELSE

IF d_counter = "101" THEN
d_counter <= "000";
ELSE
d_counter <= d_counter + "001";
END IF;

CASE d_counter IS
WHEN "000" => w_data ( 31 DOWNTO 0) <= in_word_l;
w_data (223 DOWNTO 192) <= in_word_h;
s_data <= w_data; -- sample only at word end
WHEN "001" => w_data ( 63 DOWNTO 32) <= in_word_l;
w_data (255 DOWNTO 224) <= in_word_h;
WHEN "010" => w_data ( 95 DOWNTO 64) <= in_word_l;
w_data (287 DOWNTO 256) <= in_word_h;
WHEN "011" => w_data (127 DOWNTO 96) <= in_word_l;
w_data (319 DOWNTO 288) <= in_word_h;
WHEN "100" => w_data (159 DOWNTO 128) <= in_word_l;
w_data (351 DOWNTO 320) <= in_word_h;
WHEN "101" => w_data (191 DOWNTO 160) <= in_word_l;
w_data (383 DOWNTO 352) <= in_word_h;
WHEN OTHERS => NULL;
END CASE;

END IF;
END IF;
END PROCESS;

 

 

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Scholar austin
Scholar
3,507 Views
Registered: ‎02-27-2008

Re: synch clk domains crossing advise

Jump to solution

Synchronous?

 

Are they two outputs from a CMT tile with 40 MHz input?

 

Output1 is 160 (x4), and Output2 240 (x6)?

 

If so there must be a way to transfer data between these two with no latency (except for the 4/6 alignment) by using the original 40 MHz (x1 on output3 of CMT)?

 

Obviously if you have to transfer 160 to 240 data, you could use a BRAM/FIFO, and if from 240 to 160 you cannot do that without overflow, so you need to limit the data rate generated in the 240 domain to 160.

 

Does that make sense?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

6 Replies
Scholar austin
Scholar
3,508 Views
Registered: ‎02-27-2008

Re: synch clk domains crossing advise

Jump to solution

Synchronous?

 

Are they two outputs from a CMT tile with 40 MHz input?

 

Output1 is 160 (x4), and Output2 240 (x6)?

 

If so there must be a way to transfer data between these two with no latency (except for the 4/6 alignment) by using the original 40 MHz (x1 on output3 of CMT)?

 

Obviously if you have to transfer 160 to 240 data, you could use a BRAM/FIFO, and if from 240 to 160 you cannot do that without overflow, so you need to limit the data rate generated in the 240 domain to 160.

 

Does that make sense?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

Visitor stmallios
Visitor
2,237 Views
Registered: ‎01-18-2017

Re: synch clk domains crossing advise

Jump to solution

Hello, thank you for the quick reply and help!!

 

Yes exactly, they come from the same 40Mhz CMT tile.

So , I used the original 40Mhz clk to latch the data between the 240Mhz deserializer and the 160Mhz domain and got no timing errors. Was that what you proposed?

0 Kudos
Scholar austin
Scholar
2,234 Views
Registered: ‎02-27-2008

Re: synch clk domains crossing advise

Jump to solution

Yes,

 

Shouldn't get any timing errors, as everything is synchronous.  Just needs to meet timing, which shouldn't be tough at all.

 

Congratulations!  Welcome to synchronous design (absolutely the best way to go, if at all possible).

 

I have no idea if you coded it properly, so the debugging is all on you (simulate with test bench, etc.).

 

Debugging someone else's coding is just not attractive (no me), so unless someone else is interested, it is up to you now.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Guide avrumw
Guide
2,226 Views
Registered: ‎01-23-2009

Re: synch clk domains crossing advise

Jump to solution

So , I used the original 40Mhz clk to latch the data between the 240Mhz deserializer and the 160Mhz domain and got no timing errors. Was that what you proposed?

 

Careful. You cannot use the 40MHz input clock, since that is before the MMCM. If you wanted to have access to the 40MHz clock, you would have to have the MMCM generate all three output clocks, 40MHz, 160MHz, and 240MHz.

 

However, that shouldn't be necessary. The ratio of these clocks are "normal" enough that the closest separation of edges is 2.083ns apart (in both directions). The device and tools shouldn't have any trouble doing a synchronous path in 2.083ns - just go directly from one domain to the other whenever you want to - the tools will time the paths correctly.

 

Avrum

Visitor stmallios
Visitor
2,131 Views
Registered: ‎01-18-2017

Re: synch clk domains crossing advise

Jump to solution

@austin wrote:

Yes,

 

Shouldn't get any timing errors, as everything is synchronous.  Just needs to meet timing, which shouldn't be tough at all.

 

Congratulations!  Welcome to synchronous design (absolutely the best way to go, if at all possible).

 

I have no idea if you coded it properly, so the debugging is all on you (simulate with test bench, etc.).

 

Debugging someone else's coding is just not attractive (no me), so unless someone else is interested, it is up to you now.

 

 


Thanks for your help!!!


Unfortunately this is not my design but a part of a big project that I have to optimize. Latency is crucial and timing closure for now is achieved only if I use Post route Phys Opt --agressive explore directive. So I am just starting to understand the implications of the various crossings between click domains.
For the invert crossing from 160M --> 240M, a bridge FF (@160M) is used and the following constrains.
set_max_delay -from [.......] -datapath_only 2.0
set_min_delay -to [.........] 0.2
I was wondering if I could use the same 40Mhz clk to latch the data out.

Thanks again!!

0 Kudos
Guide avrumw
Guide
2,121 Views
Registered: ‎01-23-2009

Re: synch clk domains crossing advise

Jump to solution

For the invert crossing from 160M --> 240M, a bridge FF (@160M) is used and the following constrains.
set_max_delay -from [.......] -datapath_only 2.0
set_min_delay -to [.........] 0.2

 

Don't do this. As I said, the 160MHz -> 240MHz clock crossing is already a normal 2.08ns static timing path. By using a set_max_delay -datapath_only you are instructing the tools to ignore clock skew, which is significant in this case (well more than 80ps). Your constraint can therefore end up underconstraining this path and thus leading to a failure.

 

Furthermore, you cannot mix set_max_delay -datapath_only with set_min_delay. A set_max_delay -datapath_only implies the min delay is false - I am pretty sure that cannot be overridden.

 

You do not need any constraints for this path...

 

Avrum