synthesis dcp from different grade result in different routing timing

[jiangzhk@126.com]

Hi, I'm working on an FPGA product that's using xcku040-2-e. The product is already shipped.

A few days ago the manager came and told me that he wanted to see if the whole design can work with xcku040-1-c.

So I changed the device in my build environment, tried re-generating the binary, ended up with some timing violation with the worst setup violation -0.215ns.

Here is what's interesting: In an effort to improve the timing, I created a pblock and copied a synthsis dcp from a previous directory and the result timing was quite good.

#- TIMING
#- WNS = 0.036 ns
#- WHS = 0.016 ns

But later when I ran the full process starting from the very beginning from synthsizing, the timing still fails with around 200ps violation. Then I realized the build with passing timing was using synthesis dcp from the original device which is xcku040-2-e.

To sum up:

xcku040-2-e synthesis dcp + xcku040-1-c place&routing = timing passes

xcku040-1-c synthesis dcp  + xcku040-1-c place&routing = timing failes

Can anyone shed some light on this? The netlist from xcku040-2-e synthesis dcp and xcku040-1-c synthesis dcp may be different, but they are supposed to be functionally exactly the same. So is the first combination going to work?

Thanks

[viviany]

Yes, the first combination will work.

-vivian

[jiangzhk@126.com · Accepted solution]

I just found that the first combination is actually invalid.

The speed grade information is passed to synth_design with "-part" option. Different speed grade corresponds to different timing model, this timing information is in synthesis dcp and used in implementation when the tool is trying to close timing.

That's why first combination can pass timing when the second fails.