02-13-2019 05:01 AM
I have two questions:
I want to study about the temperature effect on resource delays (LUTs and interconnects) of FPGAs. Is there any document?
Vivado timing analysis reports path delays for what temperature? Can I estimate the delay of paths for specific temperature based on the delays reported by the Vivado timing analysis?
02-13-2019 06:21 AM
Search for FPGA ring oscillator pdf's. At least a few thousand out there,
Delays are worst process, temperature, and voltage corners.
02-13-2019 06:26 AM
Hi, @farzian ,
Delay (Min or Max) will be reported with the combination of PVT factors mentioned by @lowearthorbit .
You cannot know the exact delay value with the specific temperature in Vivado.
02-13-2019 06:53 AM
"I want to study about the temperature effect on resource delays (LUTs and interconnects) of FPGAs. Is there any document?"
It depends what you are looking for. If you go back to ISE, you can use speed print on the devices along with setting the temp and voltage pro rating command to see how different temps change those numbers. Now those numbers are process numbers, so they reflect all devices for that part and speedgrade. You will find that in the static numbers at about 5 series, it doesn't make any difference.You can check out AR 32216 which comments to this.
Because of that, in Vivado, even if you print out the speed models, you will only see the difference between the FAST and SLOW corners, but you don't know what tempeature those occur at because it might not be at the very extreme temps.
"Vivado timing analysis reports path delays for what temperature? Can I estimate the delay of paths for specific temperature based on the delays reported by the Vivado timing analysis?"
When you look at the delays, those are going to be a specific corner as stated above. But the slowest point might not happen at the hottest temperature across PVT. So those are worse case numbers, not hottest numbers. Vivado does a 4 corner analysis which is a combination of the FAST/SLOW process, vs MIN/MAX delays and reports the worst combination on any given path.
Typically this is MAX at SLOW for setup, and MIN at FAST for HOLD (Which are "unrealistic" in the sense that it's unlikely that a device is going to have the data and the clocks be at opposite ends at the same time, but does well to guarantee that all devices that meet timing will work) but it checks them all, and you can report out with get_speed_models if you so desire.
But you can not expect to predict this based on temp alone. You can always measure the delays through your device yourself, and see what it is doing at a given temp.
But it would be helpful to know why you want to know the answers to these questions to begin with.
02-13-2019 08:54 AM
Your description of corners and on chip variation is not completely correct. Take a look at this post on how on chip variation is performed.
But back to the original question - Vivado does not give you (or even have) timing numbers for anything other than the 4 corners I describe in the above post ([SLOW_MAX] [SLOW_MIN] [FAST_MAX] [FAST_MIN]) and two of the four don't actually represent real process points (really only [SLOW_MAX] and [FAST_MIN] are real). Vivado does not allow for "process derating" - asking "what if I reduce one of the PVT conditions to this range?".
ISE did support it on some of the earlier technologies, but it doesn't on the later ones (I think @evant_nq is probably right that Virtex-5 was the last technology that supported it).
02-13-2019 12:08 PM
This is typicaly done by building ring oscilators on the chip,
As conditions chage , the frequency of the oscilation changes, bring this out to a IOB, and you can see if delay is increasing or decreasing as you change paramiters.
What it wont tell you, is what happens if you or the tools put the oscilator else where on the chip, and as its going to be mutlipek LUTs and touting delay, its an average of these,
And of cource, its no indication of the next chip.