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Visitor
Visitor
6,822 Views
Registered: ‎09-11-2012

test bench waveform

I HAVE A BIG PROBLEM.I AM A FINAL YEAR ENGINEERING STUDENT.XILINX 9.1ISE IS NOT SUPPORTED ON 64BIT,SO I DOWNLOADED XILINX 13.2 BUT 13.2 VERSION DONOT SUPPORT "TEST BENCH WAVEFORM".I DONOT KNOW HOW TO WRITE VHDL TEST BENCH CAN ANYONE HELP MEEEEEEEEEEE PLEASEEEEEEEEEEEEEEEEEEEE

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Professor
Professor
6,812 Views
Registered: ‎08-14-2007

From the ISE Navigator, go to Project --> New Source

 

Select VHDL Test Bench

 

Give it a name

 

Associate the test bench with the VHDL source of your project you want to simulate.

 

Click finish.

 

ISE will create a template that instantiates the entity to test (UUT) and initializes its inputs.

I believe for the VHDL test benches it also creates a process to toggle the clock signal, if

it can figure out which input is the clock.

 

Then you can edit this file to create more processes to generate the stimulus you want.

Anything you can do with waveforms can be done using simple sequential processes and

wait statements.  If you have a VHDL text book, it should give some examples.

 

-- Gabor

-- Gabor
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