04-12-2018 11:51 AM - edited 04-12-2018 12:05 PM
Hi, please, how can I find out the minimum clock period (the maximum clock frequency in MHz) of a Radix-8 booth mulitplier? After the synthesizing and implementation I got the following:
Asynchronous Control Signals Information:
No asynchronous control signals found in this design
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: 15.397ns
Maximum output required time after clock: 0.562ns
Maximum combinational path delay: No path found
Is there any way to know the minimum clock period ? Thanks :)
04-13-2018 04:15 AM
The only thing you can do is to constrain your clock to a frequency and implement your design. If there are no timing errors, increase your clock frequency and try again. Be aware that timing is implementation dependent and as you change the design and add to the FPGA, the timing will change.
04-17-2018 03:14 AM
04-18-2018 11:57 AM
I agree with the approach suggested by @bruce_karaffa.
However to really get this right, you need to ensure that the part of the design you are looking to get the performance of is entirely between flip-flops. It looks like your multiplier is from combinatorial inputs to internal flip-flops - this makes is more difficult. You should wrap the module in another layer that has flip-flops between the inputs and the combinatorial logic.
In Vivado (not in ISE), synthesis (and even implementation, in some famlies) can be done "out-of-context (OOC)". This can be quite useful since the tool does not try to connect inputs to input pins of the FPGA and output pins of the FPGA...