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the minimum clock period of a multiplier

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Visitor
Posts: 2
Registered: ‎04-10-2018

the minimum clock period of a multiplier

[ Edited ]

Hi, please, how can I find out the minimum clock period (the maximum clock frequency in MHz) of a Radix-8 booth mulitplier? After the synthesizing and implementation I got the following:

 

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

 

Timing Summary:
---------------

Speed Grade: -3

Minimum period: No path found

Minimum input arrival time before clock: 15.397ns

Maximum output required time after clock: 0.562ns

Maximum combinational path delay: No path found

 

Is there any way to know the minimum clock period ? Thanks :)

Scholar
Posts: 451
Registered: ‎06-21-2017

Re: the minimum clock period of a multiplier

The only thing you can do is to constrain your clock to a frequency and implement your design.  If there are no timing errors, increase your clock frequency and try again.  Be aware that timing is implementation dependent and as you change the design and add to the FPGA, the timing will change.

Moderator
Posts: 1,617
Registered: ‎01-16-2013

Re: the minimum clock period of a multiplier

Hi,

There is no direct way to report out max frequency.
As bruce_karaffa suggested you should have specification about clock frequency which you can provide as constraints and then check for post-implementation timing summary.

Also I would like to add there is also impact of timing constraints at synthesis phase also.

Thanks,
Yash
Historian
Posts: 4,559
Registered: ‎01-23-2009

Re: the minimum clock period of a multiplier

I agree with the approach suggested by @bruce_karaffa.

 

However to really get this right, you need to ensure that the part of the design you are looking to get the performance of is entirely between flip-flops. It looks like your multiplier is from combinatorial inputs to internal flip-flops - this makes is more difficult. You should wrap the module in another layer that has flip-flops between the inputs and the combinatorial logic.

 

In Vivado (not in ISE), synthesis (and even implementation, in some famlies) can be done "out-of-context (OOC)". This can be quite useful since the tool does not try to connect inputs to input pins of the FPGA and output pins of the FPGA...

 

Avrum