i am using virtex-4 fx 100t, my application is related to ethernet, i am using ethernet lite ip core,
i hav created a edk project with ethernet ip core added, later i hav instantiated edk into ise environment ,
here in ise i am unable to meet couple of timing constaints,
1. Timing Constaint: TS RXIN_generic etherne_10_100 = maxdelay from TIMEGRP "PADS" to TIMEGRP "RXCLK_generic_ethernet_10_100" 6 ns
data path delay = 8.176 ns
where as requirement is 6 ns
slake = - 2.176ns
so pls kindly help me out in solving this issue
due to these timing constaints i was unable to achieve proper communication over ethernet.
This is not the correct constraint for constraining FPGA inputs. Please see the section on OFFSET IN constraints in the ISE Constraints Guide.