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Adventurer
Adventurer
655 Views
Registered: ‎07-27-2010

timing constraint are not met

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Hi

 

I have written code which is successfully synthesized and implemented

But it does not meet its timing constraint

the timing constraint is defined as

 create_clock -name clk -period 10.000 [get_ports clk]  (by default)

 

and I get WNS -54.990

and TNS -14004.539

 

What is the possible reason and how can I correct it

Regards

Uzmeed

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Explorer
Explorer
528 Views
Registered: ‎06-28-2018

Re: timing constraint are not met

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Hi @uzmeed 

Arithmetic and logic operations in your HDL code are implemented using look up tables (LUT), shift registers and other logic elements inside configurable logic blocks (CLB) or specialized hardware such as digital signal processor (DSP) blocks on the FPGA.

In a clocked system, data usually moves from one clocked element such as a flip-flop (FF) to another in one (or more) clock period. For FFs to successfully capture the data on their inputs we have to satisfy setup (and hold) time requirements of these elements, which means that the data at their input should be stable for some amount of time before the capturing clock edge arrives. If you are doing some operations on the data it must pass through some asynchronous logic elements such as LUTs. A LUT is basically a memory element that stores the possible outcomes of an operation. If you are doing a simple logic operation on six 1-bit signals then a 6-input LUT will be used. If you increase the number or the size of the signals then the number of LUTs you have to use will increase since they are fixed hardware and have limited number of inputs. These elements are separated from each other by a certain distance so the signals need some time to travel from one LUT to another and there is also logic delay on each of these elements. If number of the elements on the datapath exceeds a certain value the data cannot reach at the destination inside the allowed time frame.

In your case, the number of these elements is around 374 for some datapaths. This is the number of elements between two flip-flops (the source and destination registers) that are clocked by the same clock source. Pipelining in HDL design is basically adding extra registers into the datapath. Instead of doing 10 operations in one clock cycle you can spend 10 clock cycles and do only 1 operation in each cycle. After each operation, you store the result on a flip-flop and on the next cycle the operation continues using this stored value. This way, number of logic elements between any two flip-flops decreases and operations can finish in one clock period. Also, every functional block in the datapath is busy operating on a different dataset so there is no decrease in the throughput, there is only a small delay of 9-10 clock cycles.

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Highlighted
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Registered: ‎06-21-2017

Re: timing constraint are not met

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You need to post the timing report.

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Adventurer
Adventurer
593 Views
Registered: ‎07-27-2010

Re: timing constraint are not met

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Hi

timing report is attached 

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Explorer
Explorer
583 Views
Registered: ‎06-28-2018

Re: timing constraint are not met

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Hi @uzmeed 

In your timing report it says (in several places)

Logic Levels:           374  (CARRY4=332 LUT1=42)

which means you are trying to do many things in one clock cycle so you cannot run the design at the specified clock frequency. Please try to pipeline the operations or use a slower clock. But a logic level of 374 shows that you're doing something wrong.

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Adventurer
Adventurer
553 Views
Registered: ‎07-27-2010

Re: timing constraint are not met

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Hi

I could not understand it completely 

Do you mean to say that many modules are run in same clock or same module doing many things in same clock 

and how can I do the pipelining

Regards

Uzmeed

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Explorer
Explorer
529 Views
Registered: ‎06-28-2018

Re: timing constraint are not met

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Hi @uzmeed 

Arithmetic and logic operations in your HDL code are implemented using look up tables (LUT), shift registers and other logic elements inside configurable logic blocks (CLB) or specialized hardware such as digital signal processor (DSP) blocks on the FPGA.

In a clocked system, data usually moves from one clocked element such as a flip-flop (FF) to another in one (or more) clock period. For FFs to successfully capture the data on their inputs we have to satisfy setup (and hold) time requirements of these elements, which means that the data at their input should be stable for some amount of time before the capturing clock edge arrives. If you are doing some operations on the data it must pass through some asynchronous logic elements such as LUTs. A LUT is basically a memory element that stores the possible outcomes of an operation. If you are doing a simple logic operation on six 1-bit signals then a 6-input LUT will be used. If you increase the number or the size of the signals then the number of LUTs you have to use will increase since they are fixed hardware and have limited number of inputs. These elements are separated from each other by a certain distance so the signals need some time to travel from one LUT to another and there is also logic delay on each of these elements. If number of the elements on the datapath exceeds a certain value the data cannot reach at the destination inside the allowed time frame.

In your case, the number of these elements is around 374 for some datapaths. This is the number of elements between two flip-flops (the source and destination registers) that are clocked by the same clock source. Pipelining in HDL design is basically adding extra registers into the datapath. Instead of doing 10 operations in one clock cycle you can spend 10 clock cycles and do only 1 operation in each cycle. After each operation, you store the result on a flip-flop and on the next cycle the operation continues using this stored value. This way, number of logic elements between any two flip-flops decreases and operations can finish in one clock period. Also, every functional block in the datapath is busy operating on a different dataset so there is no decrease in the throughput, there is only a small delay of 9-10 clock cycles.

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Adventurer
Adventurer
465 Views
Registered: ‎07-27-2010

Re: timing constraint are not met

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Hi @baltintop 

Thank you much for your detailed reply 

From the timing report can we figure out the signals that are causing delays 

Regards

Uzmeed

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Explorer
Explorer
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Registered: ‎06-28-2018

Re: timing constraint are not met

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@uzmeed 

Yes, signal names are visible in the timing report. I suggest using Vivado GUI to examine the report.

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: timing constraint are not met

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When you design an FPGA, your designing logic.
To gets the best out of FPGAs you need to design logic,

what language are you using to design the FPGA ?
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